1*4882a593Smuzhiyun* UART (Universal Asynchronous Receiver/Transmitter) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : one of: 5*4882a593Smuzhiyun - "ns8250" 6*4882a593Smuzhiyun - "ns16450" 7*4882a593Smuzhiyun - "ns16550a" 8*4882a593Smuzhiyun - "ns16550" 9*4882a593Smuzhiyun - "ns16750" 10*4882a593Smuzhiyun - "ns16850" 11*4882a593Smuzhiyun - For Tegra20, must contain "nvidia,tegra20-uart" 12*4882a593Smuzhiyun - For other Tegra, must contain '"nvidia,<chip>-uart", 13*4882a593Smuzhiyun "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124, 14*4882a593Smuzhiyun tegra132, or tegra210. 15*4882a593Smuzhiyun - "nxp,lpc3220-uart" 16*4882a593Smuzhiyun - "ralink,rt2880-uart" 17*4882a593Smuzhiyun - "ibm,qpace-nwp-serial" 18*4882a593Smuzhiyun - "altr,16550-FIFO32" 19*4882a593Smuzhiyun - "altr,16550-FIFO64" 20*4882a593Smuzhiyun - "altr,16550-FIFO128" 21*4882a593Smuzhiyun - "fsl,16550-FIFO64" 22*4882a593Smuzhiyun - "fsl,ns16550" 23*4882a593Smuzhiyun - "serial" if the port type is unknown. 24*4882a593Smuzhiyun- reg : offset and length of the register set for the device. 25*4882a593Smuzhiyun- interrupts : should contain uart interrupt. 26*4882a593Smuzhiyun- clock-frequency : the input clock frequency for the UART 27*4882a593Smuzhiyun or 28*4882a593Smuzhiyun clocks phandle to refer to the clk used as per Documentation/devicetree 29*4882a593Smuzhiyun /bindings/clock/clock-bindings.txt 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunOptional properties: 32*4882a593Smuzhiyun- current-speed : the current active speed of the UART. 33*4882a593Smuzhiyun- reg-offset : offset to apply to the mapbase from the start of the registers. 34*4882a593Smuzhiyun- reg-shift : quantity to shift the register offsets by. 35*4882a593Smuzhiyun- reg-io-width : the size (in bytes) of the IO accesses that should be 36*4882a593Smuzhiyun performed on the device. There are some systems that require 32-bit 37*4882a593Smuzhiyun accesses to the UART (e.g. TI davinci). 38*4882a593Smuzhiyun- used-by-rtas : set to indicate that the port is in use by the OpenFirmware 39*4882a593Smuzhiyun RTAS and should not be registered. 40*4882a593Smuzhiyun- no-loopback-test: set to indicate that the port does not implements loopback 41*4882a593Smuzhiyun test mode 42*4882a593Smuzhiyun- fifo-size: the fifo size of the UART. 43*4882a593Smuzhiyun- auto-flow-control: one way to enable automatic flow control support. The 44*4882a593Smuzhiyun driver is allowed to detect support for the capability even without this 45*4882a593Smuzhiyun property. 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunNote: 48*4882a593Smuzhiyun* fsl,ns16550: 49*4882a593Smuzhiyun ------------ 50*4882a593Smuzhiyun Freescale DUART is very similar to the PC16552D (and to a 51*4882a593Smuzhiyun pair of NS16550A), albeit with some nonstandard behavior such as 52*4882a593Smuzhiyun erratum A-004737 (relating to incorrect BRK handling). 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun Represents a single port that is compatible with the DUART found 55*4882a593Smuzhiyun on many Freescale chips (examples include mpc8349, mpc8548, 56*4882a593Smuzhiyun mpc8641d, p4080 and ls2080a). 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunExample: 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun uart@80230000 { 61*4882a593Smuzhiyun compatible = "ns8250"; 62*4882a593Smuzhiyun reg = <0x80230000 0x100>; 63*4882a593Smuzhiyun clock-frequency = <3686400>; 64*4882a593Smuzhiyun interrupts = <10>; 65*4882a593Smuzhiyun reg-shift = <2>; 66*4882a593Smuzhiyun }; 67