1*4882a593SmuzhiyunST, stm32 flexible memory controller Drive 2*4882a593SmuzhiyunRequired properties: 3*4882a593Smuzhiyun- compatible : "st,stm32-fmc" 4*4882a593Smuzhiyun- reg : fmc controller base address 5*4882a593Smuzhiyun- clocks : fmc controller clock 6*4882a593Smuzhiyunu-boot,dm-pre-reloc: flag to initialize memory before relocation. 7*4882a593Smuzhiyun 8*4882a593Smuzhiyunon-board sdram memory attributes: 9*4882a593Smuzhiyun- st,sdram-control : parameters for sdram configuration, in this order: 10*4882a593Smuzhiyun number of columns 11*4882a593Smuzhiyun number of rows 12*4882a593Smuzhiyun memory width 13*4882a593Smuzhiyun number of intenal banks in memory 14*4882a593Smuzhiyun cas latency 15*4882a593Smuzhiyun read burst enable or disable 16*4882a593Smuzhiyun read pipe delay 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- st,sdram-timing: timings for sdram, in this order: 19*4882a593Smuzhiyun tmrd 20*4882a593Smuzhiyun txsr 21*4882a593Smuzhiyun tras 22*4882a593Smuzhiyun trc 23*4882a593Smuzhiyun trp 24*4882a593Smuzhiyun trcd 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunThere is device tree include file at : 27*4882a593Smuzhiyuninclude/dt-bindings/memory/stm32-sdram.h to define sdram control and timing 28*4882a593Smuzhiyunparameters as MACROS. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunExample: 31*4882a593Smuzhiyun fmc: fmc@A0000000 { 32*4882a593Smuzhiyun compatible = "st,stm32-fmc"; 33*4882a593Smuzhiyun reg = <0xA0000000 0x1000>; 34*4882a593Smuzhiyun clocks = <&rcc 0 64>; 35*4882a593Smuzhiyun u-boot,dm-pre-reloc; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun &fmc { 39*4882a593Smuzhiyun pinctrl-0 = <&fmc_pins>; 40*4882a593Smuzhiyun pinctrl-names = "default"; 41*4882a593Smuzhiyun status = "okay"; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* sdram memory configuration from sdram datasheet */ 44*4882a593Smuzhiyun bank1: bank@0 { 45*4882a593Smuzhiyun st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 46*4882a593Smuzhiyun CAS_3 RD_BURST_EN RD_PIPE_DL_0>; 47*4882a593Smuzhiyun st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 48*4882a593Smuzhiyun TRCD_18>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* sdram memory configuration from sdram datasheet */ 52*4882a593Smuzhiyun bank2: bank@1 { 53*4882a593Smuzhiyun st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 54*4882a593Smuzhiyun CAS_3 RD_BURST_EN RD_PIPE_DL_0>; 55*4882a593Smuzhiyun st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 56*4882a593Smuzhiyun TRCD_18>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun } 59