1*4882a593Smuzhiyun== Introduction == 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunHardware modules that control pin multiplexing or configuration parameters 4*4882a593Smuzhiyunsuch as pull-up/down, tri-state, drive-strength etc are designated as pin 5*4882a593Smuzhiyuncontrollers. Each pin controller must be represented as a node in device tree, 6*4882a593Smuzhiyunjust like any other hardware module. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunHardware modules whose signals are affected by pin configuration are 9*4882a593Smuzhiyundesignated client devices. Again, each client device must be represented as a 10*4882a593Smuzhiyunnode in device tree, just like any other hardware module. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunFor a client device to operate correctly, certain pin controllers must 13*4882a593Smuzhiyunset up certain specific pin configurations. Some client devices need a 14*4882a593Smuzhiyunsingle static pin configuration, e.g. set up during initialization. Others 15*4882a593Smuzhiyunneed to reconfigure pins at run-time, for example to tri-state pins when the 16*4882a593Smuzhiyundevice is inactive. Hence, each client device can define a set of named 17*4882a593Smuzhiyunstates. The number and names of those states is defined by the client device's 18*4882a593Smuzhiyunown binding. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunThe common pinctrl bindings defined in this file provide an infrastructure 21*4882a593Smuzhiyunfor client device device tree nodes to map those state names to the pin 22*4882a593Smuzhiyunconfiguration used by those states. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunNote that pin controllers themselves may also be client devices of themselves. 25*4882a593SmuzhiyunFor example, a pin controller may set up its own "active" state when the 26*4882a593Smuzhiyundriver loads. This would allow representing a board's static pin configuration 27*4882a593Smuzhiyunin a single place, rather than splitting it across multiple client device 28*4882a593Smuzhiyunnodes. The decision to do this or not somewhat rests with the author of 29*4882a593Smuzhiyunindividual board device tree files, and any requirements imposed by the 30*4882a593Smuzhiyunbindings for the individual client devices in use by that board, i.e. whether 31*4882a593Smuzhiyunthey require certain specific named states for dynamic pin configuration. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun== Pinctrl client devices == 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunFor each client device individually, every pin state is assigned an integer 36*4882a593SmuzhiyunID. These numbers start at 0, and are contiguous. For each state ID, a unique 37*4882a593Smuzhiyunproperty exists to define the pin configuration. Each state may also be 38*4882a593Smuzhiyunassigned a name. When names are used, another property exists to map from 39*4882a593Smuzhiyunthose names to the integer IDs. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunEach client device's own binding determines the set of states that must be 42*4882a593Smuzhiyundefined in its device tree node, and whether to define the set of state 43*4882a593SmuzhiyunIDs that must be provided, or whether to define the set of state names that 44*4882a593Smuzhiyunmust be provided. 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunRequired properties: 47*4882a593Smuzhiyunpinctrl-0: List of phandles, each pointing at a pin configuration 48*4882a593Smuzhiyun node. These referenced pin configuration nodes must be child 49*4882a593Smuzhiyun nodes of the pin controller that they configure. Multiple 50*4882a593Smuzhiyun entries may exist in this list so that multiple pin 51*4882a593Smuzhiyun controllers may be configured, or so that a state may be built 52*4882a593Smuzhiyun from multiple nodes for a single pin controller, each 53*4882a593Smuzhiyun contributing part of the overall configuration. See the next 54*4882a593Smuzhiyun section of this document for details of the format of these 55*4882a593Smuzhiyun pin configuration nodes. 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun In some cases, it may be useful to define a state, but for it 58*4882a593Smuzhiyun to be empty. This may be required when a common IP block is 59*4882a593Smuzhiyun used in an SoC either without a pin controller, or where the 60*4882a593Smuzhiyun pin controller does not affect the HW module in question. If 61*4882a593Smuzhiyun the binding for that IP block requires certain pin states to 62*4882a593Smuzhiyun exist, they must still be defined, but may be left empty. 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunOptional properties: 65*4882a593Smuzhiyunpinctrl-1: List of phandles, each pointing at a pin configuration 66*4882a593Smuzhiyun node within a pin controller. 67*4882a593Smuzhiyun... 68*4882a593Smuzhiyunpinctrl-n: List of phandles, each pointing at a pin configuration 69*4882a593Smuzhiyun node within a pin controller. 70*4882a593Smuzhiyunpinctrl-names: The list of names to assign states. List entry 0 defines the 71*4882a593Smuzhiyun name for integer state ID 0, list entry 1 for state ID 1, and 72*4882a593Smuzhiyun so on. 73*4882a593Smuzhiyun 74*4882a593SmuzhiyunFor example: 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* For a client device requiring named states */ 77*4882a593Smuzhiyun device { 78*4882a593Smuzhiyun pinctrl-names = "active", "idle"; 79*4882a593Smuzhiyun pinctrl-0 = <&state_0_node_a>; 80*4882a593Smuzhiyun pinctrl-1 = <&state_1_node_a &state_1_node_b>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* For the same device if using state IDs */ 84*4882a593Smuzhiyun device { 85*4882a593Smuzhiyun pinctrl-0 = <&state_0_node_a>; 86*4882a593Smuzhiyun pinctrl-1 = <&state_1_node_a &state_1_node_b>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* 90*4882a593Smuzhiyun * For an IP block whose binding supports pin configuration, 91*4882a593Smuzhiyun * but in use on an SoC that doesn't have any pin control hardware 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun device { 94*4882a593Smuzhiyun pinctrl-names = "active", "idle"; 95*4882a593Smuzhiyun pinctrl-0 = <>; 96*4882a593Smuzhiyun pinctrl-1 = <>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun== Pin controller devices == 100*4882a593Smuzhiyun 101*4882a593SmuzhiyunPin controller devices should contain the pin configuration nodes that client 102*4882a593Smuzhiyundevices reference. 103*4882a593Smuzhiyun 104*4882a593SmuzhiyunFor example: 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun pincontroller { 107*4882a593Smuzhiyun ... /* Standard DT properties for the device itself elided */ 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun state_0_node_a { 110*4882a593Smuzhiyun ... 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun state_1_node_a { 113*4882a593Smuzhiyun ... 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun state_1_node_b { 116*4882a593Smuzhiyun ... 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun } 119*4882a593Smuzhiyun 120*4882a593SmuzhiyunThe contents of each of those pin configuration child nodes is defined 121*4882a593Smuzhiyunentirely by the binding for the individual pin controller device. There 122*4882a593Smuzhiyunexists no common standard for this content. 123*4882a593Smuzhiyun 124*4882a593SmuzhiyunThe pin configuration nodes need not be direct children of the pin controller 125*4882a593Smuzhiyundevice; they may be grandchildren, for example. Whether this is legal, and 126*4882a593Smuzhiyunwhether there is any interaction between the child and intermediate parent 127*4882a593Smuzhiyunnodes, is again defined entirely by the binding for the individual pin 128*4882a593Smuzhiyuncontroller device. 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun== Generic pin multiplexing node content == 131*4882a593Smuzhiyun 132*4882a593Smuzhiyunpin multiplexing nodes: 133*4882a593Smuzhiyun 134*4882a593Smuzhiyunfunction - the mux function to select 135*4882a593Smuzhiyungroups - the list of groups to select with this function 136*4882a593Smuzhiyun (either this or "pins" must be specified) 137*4882a593Smuzhiyunpins - the list of pins to select with this function (either 138*4882a593Smuzhiyun this or "groups" must be specified) 139*4882a593Smuzhiyun 140*4882a593SmuzhiyunExample: 141*4882a593Smuzhiyun 142*4882a593Smuzhiyunstate_0_node_a { 143*4882a593Smuzhiyun uart0 { 144*4882a593Smuzhiyun function = "uart0"; 145*4882a593Smuzhiyun groups = "u0rxtx", "u0rtscts"; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun}; 148*4882a593Smuzhiyunstate_1_node_a { 149*4882a593Smuzhiyun spi0 { 150*4882a593Smuzhiyun function = "spi0"; 151*4882a593Smuzhiyun groups = "spi0pins"; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun}; 154*4882a593Smuzhiyunstate_2_node_a { 155*4882a593Smuzhiyun function = "i2c0"; 156*4882a593Smuzhiyun pins = "mfio29", "mfio30"; 157*4882a593Smuzhiyun}; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun== Generic pin configuration node content == 160*4882a593Smuzhiyun 161*4882a593SmuzhiyunMany data items that are represented in a pin configuration node are common 162*4882a593Smuzhiyunand generic. Pin control bindings should use the properties defined below 163*4882a593Smuzhiyunwhere they are applicable; not all of these properties are relevant or useful 164*4882a593Smuzhiyunfor all hardware or binding structures. Each individual binding document 165*4882a593Smuzhiyunshould state which of these generic properties, if any, are used, and the 166*4882a593Smuzhiyunstructure of the DT nodes that contain these properties. 167*4882a593Smuzhiyun 168*4882a593SmuzhiyunSupported generic properties are: 169*4882a593Smuzhiyun 170*4882a593Smuzhiyunpins - the list of pins that properties in the node 171*4882a593Smuzhiyun apply to (either this or "group" has to be 172*4882a593Smuzhiyun specified) 173*4882a593Smuzhiyungroup - the group to apply the properties to, if the driver 174*4882a593Smuzhiyun supports configuration of whole groups rather than 175*4882a593Smuzhiyun individual pins (either this or "pins" has to be 176*4882a593Smuzhiyun specified) 177*4882a593Smuzhiyunbias-disable - disable any pin bias 178*4882a593Smuzhiyunbias-high-impedance - high impedance mode ("third-state", "floating") 179*4882a593Smuzhiyunbias-bus-hold - latch weakly 180*4882a593Smuzhiyunbias-pull-up - pull up the pin 181*4882a593Smuzhiyunbias-pull-down - pull down the pin 182*4882a593Smuzhiyunbias-pull-pin-default - use pin-default pull state 183*4882a593Smuzhiyundrive-push-pull - drive actively high and low 184*4882a593Smuzhiyundrive-open-drain - drive with open drain 185*4882a593Smuzhiyundrive-open-source - drive with open source 186*4882a593Smuzhiyundrive-strength - sink or source at most X mA 187*4882a593Smuzhiyuninput-enable - enable input on pin (no effect on output) 188*4882a593Smuzhiyuninput-disable - disable input on pin (no effect on output) 189*4882a593Smuzhiyuninput-schmitt-enable - enable schmitt-trigger mode 190*4882a593Smuzhiyuninput-schmitt-disable - disable schmitt-trigger mode 191*4882a593Smuzhiyuninput-debounce - debounce mode with debound time X 192*4882a593Smuzhiyunpower-source - select between different power supplies 193*4882a593Smuzhiyunlow-power-enable - enable low power mode 194*4882a593Smuzhiyunlow-power-disable - disable low power mode 195*4882a593Smuzhiyunoutput-low - set the pin to output mode with low level 196*4882a593Smuzhiyunoutput-high - set the pin to output mode with high level 197*4882a593Smuzhiyunslew-rate - set the slew rate 198*4882a593Smuzhiyun 199*4882a593SmuzhiyunFor example: 200*4882a593Smuzhiyun 201*4882a593Smuzhiyunstate_0_node_a { 202*4882a593Smuzhiyun cts_rxd { 203*4882a593Smuzhiyun pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ 204*4882a593Smuzhiyun bias-pull-up; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun}; 207*4882a593Smuzhiyunstate_1_node_a { 208*4882a593Smuzhiyun rts_txd { 209*4882a593Smuzhiyun pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ 210*4882a593Smuzhiyun output-high; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun}; 213*4882a593Smuzhiyunstate_2_node_a { 214*4882a593Smuzhiyun foo { 215*4882a593Smuzhiyun group = "foo-group"; 216*4882a593Smuzhiyun bias-pull-up; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun}; 219*4882a593Smuzhiyun 220*4882a593SmuzhiyunSome of the generic properties take arguments. For those that do, the 221*4882a593Smuzhiyunarguments are described below. 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun- pins takes a list of pin names or IDs as a required argument. The specific 224*4882a593Smuzhiyun binding for the hardware defines: 225*4882a593Smuzhiyun - Whether the entries are integers or strings, and their meaning. 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun- bias-pull-up, -down and -pin-default take as optional argument on hardware 228*4882a593Smuzhiyun supporting it the pull strength in Ohm. bias-disable will disable the pull. 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun- drive-strength takes as argument the target strength in mA. 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun- input-debounce takes the debounce time in usec as argument 233*4882a593Smuzhiyun or 0 to disable debouncing 234*4882a593Smuzhiyun 235*4882a593SmuzhiyunMore in-depth documentation on these parameters can be found in 236*4882a593Smuzhiyun<include/linux/pinctrl/pinconf-generic.h> 237