1*4882a593Smuzhiyun* Altera Triple-Speed Ethernet MAC driver (TSE) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should 5*4882a593Smuzhiyun be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE. 6*4882a593Smuzhiyun- reg: Address and length of the register set for the device. It contains 7*4882a593Smuzhiyun the information of registers in the same order as described by reg-names 8*4882a593Smuzhiyun- reg-names: Should contain the reg names 9*4882a593Smuzhiyun "control_port": MAC configuration space region 10*4882a593Smuzhiyun "tx_csr": xDMA Tx dispatcher control and status space region 11*4882a593Smuzhiyun "tx_desc": MSGDMA Tx dispatcher descriptor space region 12*4882a593Smuzhiyun "rx_csr" : xDMA Rx dispatcher control and status space region 13*4882a593Smuzhiyun "rx_desc": MSGDMA Rx dispatcher descriptor space region 14*4882a593Smuzhiyun "rx_resp": MSGDMA Rx dispatcher response space region 15*4882a593Smuzhiyun "s1": SGDMA descriptor memory 16*4882a593Smuzhiyun- interrupts: Should contain the TSE interrupts and it's mode. 17*4882a593Smuzhiyun- interrupt-names: Should contain the interrupt names 18*4882a593Smuzhiyun "rx_irq": xDMA Rx dispatcher interrupt 19*4882a593Smuzhiyun "tx_irq": xDMA Tx dispatcher interrupt 20*4882a593Smuzhiyun- rx-fifo-depth: MAC receive FIFO buffer depth in bytes 21*4882a593Smuzhiyun- tx-fifo-depth: MAC transmit FIFO buffer depth in bytes 22*4882a593Smuzhiyun- phy-mode: See ethernet.txt in the same directory. 23*4882a593Smuzhiyun- phy-handle: See ethernet.txt in the same directory. 24*4882a593Smuzhiyun- phy-addr: See ethernet.txt in the same directory. A configuration should 25*4882a593Smuzhiyun include phy-handle or phy-addr. 26*4882a593Smuzhiyun- altr,has-supplementary-unicast: 27*4882a593Smuzhiyun If present, TSE supports additional unicast addresses. 28*4882a593Smuzhiyun Otherwise additional unicast addresses are not supported. 29*4882a593Smuzhiyun- altr,has-hash-multicast-filter: 30*4882a593Smuzhiyun If present, TSE supports a hash based multicast filter. 31*4882a593Smuzhiyun Otherwise, hash-based multicast filtering is not supported. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun- mdio device tree subnode: When the TSE has a phy connected to its local 34*4882a593Smuzhiyun mdio, there must be device tree subnode with the following 35*4882a593Smuzhiyun required properties: 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun - compatible: Must be "altr,tse-mdio". 38*4882a593Smuzhiyun - #address-cells: Must be <1>. 39*4882a593Smuzhiyun - #size-cells: Must be <0>. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun For each phy on the mdio bus, there must be a node with the following 42*4882a593Smuzhiyun fields: 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun - reg: phy id used to communicate to phy. 45*4882a593Smuzhiyun - device_type: Must be "ethernet-phy". 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunOptional properties: 48*4882a593Smuzhiyun- local-mac-address: See ethernet.txt in the same directory. 49*4882a593Smuzhiyun- max-frame-size: See ethernet.txt in the same directory. 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunExample: 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun tse_sub_0_eth_tse_0: ethernet@0x1,00000000 { 54*4882a593Smuzhiyun compatible = "altr,tse-msgdma-1.0"; 55*4882a593Smuzhiyun reg = <0x00000001 0x00000000 0x00000400>, 56*4882a593Smuzhiyun <0x00000001 0x00000460 0x00000020>, 57*4882a593Smuzhiyun <0x00000001 0x00000480 0x00000020>, 58*4882a593Smuzhiyun <0x00000001 0x000004A0 0x00000008>, 59*4882a593Smuzhiyun <0x00000001 0x00000400 0x00000020>, 60*4882a593Smuzhiyun <0x00000001 0x00000420 0x00000020>; 61*4882a593Smuzhiyun reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; 62*4882a593Smuzhiyun interrupt-parent = <&hps_0_arm_gic_0>; 63*4882a593Smuzhiyun interrupts = <0 41 4>, <0 40 4>; 64*4882a593Smuzhiyun interrupt-names = "rx_irq", "tx_irq"; 65*4882a593Smuzhiyun rx-fifo-depth = <2048>; 66*4882a593Smuzhiyun tx-fifo-depth = <2048>; 67*4882a593Smuzhiyun address-bits = <48>; 68*4882a593Smuzhiyun max-frame-size = <1500>; 69*4882a593Smuzhiyun local-mac-address = [ 00 00 00 00 00 00 ]; 70*4882a593Smuzhiyun phy-mode = "gmii"; 71*4882a593Smuzhiyun altr,has-supplementary-unicast; 72*4882a593Smuzhiyun altr,has-hash-multicast-filter; 73*4882a593Smuzhiyun phy-handle = <&phy0>; 74*4882a593Smuzhiyun mdio { 75*4882a593Smuzhiyun compatible = "altr,tse-mdio"; 76*4882a593Smuzhiyun #address-cells = <1>; 77*4882a593Smuzhiyun #size-cells = <0>; 78*4882a593Smuzhiyun phy0: ethernet-phy@0 { 79*4882a593Smuzhiyun reg = <0x0>; 80*4882a593Smuzhiyun device_type = "ethernet-phy"; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun phy1: ethernet-phy@1 { 84*4882a593Smuzhiyun reg = <0x1>; 85*4882a593Smuzhiyun device_type = "ethernet-phy"; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun tse_sub_1_eth_tse_0: ethernet@0x1,00001000 { 92*4882a593Smuzhiyun compatible = "altr,tse-msgdma-1.0"; 93*4882a593Smuzhiyun reg = <0x00000001 0x00001000 0x00000400>, 94*4882a593Smuzhiyun <0x00000001 0x00001460 0x00000020>, 95*4882a593Smuzhiyun <0x00000001 0x00001480 0x00000020>, 96*4882a593Smuzhiyun <0x00000001 0x000014A0 0x00000008>, 97*4882a593Smuzhiyun <0x00000001 0x00001400 0x00000020>, 98*4882a593Smuzhiyun <0x00000001 0x00001420 0x00000020>; 99*4882a593Smuzhiyun reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; 100*4882a593Smuzhiyun interrupt-parent = <&hps_0_arm_gic_0>; 101*4882a593Smuzhiyun interrupts = <0 43 4>, <0 42 4>; 102*4882a593Smuzhiyun interrupt-names = "rx_irq", "tx_irq"; 103*4882a593Smuzhiyun rx-fifo-depth = <2048>; 104*4882a593Smuzhiyun tx-fifo-depth = <2048>; 105*4882a593Smuzhiyun address-bits = <48>; 106*4882a593Smuzhiyun max-frame-size = <1500>; 107*4882a593Smuzhiyun local-mac-address = [ 00 00 00 00 00 00 ]; 108*4882a593Smuzhiyun phy-mode = "gmii"; 109*4882a593Smuzhiyun altr,has-supplementary-unicast; 110*4882a593Smuzhiyun altr,has-hash-multicast-filter; 111*4882a593Smuzhiyun phy-handle = <&phy1>; 112*4882a593Smuzhiyun }; 113