1*4882a593SmuzhiyunNAND Flash 2*4882a593Smuzhiyun---------- 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun(there isn't yet a generic binding in Linux, so this describes what is in 5*4882a593SmuzhiyunU-Boot. There should not be Linux-specific or U-Boot specific binding, just 6*4882a593Smuzhiyuna binding that describes this hardware. But agreeing a binding in Linux in 7*4882a593Smuzhiyunthe absence of a driver may be beyond my powers.) 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThe device node for a NAND flash device is as follows: 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRequired properties : 12*4882a593Smuzhiyun - compatible : Should be "manufacturer,device", "nand-flash" 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunThis node should sit inside its controller. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunNvidia NAND Controller 18*4882a593Smuzhiyun---------------------- 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunThe device node for a NAND flash controller is as follows: 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunOptional properties: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunnvidia,wp-gpios : GPIO of write-protect line, three cells in the format: 25*4882a593Smuzhiyun phandle, parameter, flags 26*4882a593Smuzhiyunnvidia,nand-width : bus width of the NAND device in bits 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns. 29*4882a593Smuzhiyun Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH), 30*4882a593Smuzhiyun TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun MAX_TRP_TREA is: 33*4882a593Smuzhiyun non-EDO mode: Max(tRP, tREA) + 6ns 34*4882a593Smuzhiyun EDO mode: tRP timing 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunThe 'reg' property should provide the chip select used by the flash chip. 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunExample 40*4882a593Smuzhiyun------- 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunnand-controller@0x70008000 { 43*4882a593Smuzhiyun compatible = "nvidia,tegra20-nand"; 44*4882a593Smuzhiyun #address-cells = <1>; 45*4882a593Smuzhiyun #size-cells = <0>; 46*4882a593Smuzhiyun nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */ 47*4882a593Smuzhiyun nvidia,nand-width = <8>; 48*4882a593Smuzhiyun nvidia,timing = <26 100 20 80 20 10 12 10 70>; 49*4882a593Smuzhiyun nand@0 { 50*4882a593Smuzhiyun reg = <0>; 51*4882a593Smuzhiyun compatible = "hynix,hy27uf4g2b", "nand-flash"; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun}; 54