1*4882a593SmuzhiyunIntel LPC Device Binding 2*4882a593Smuzhiyun======================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe device tree node which describes the operation of the Intel Low Pin 5*4882a593SmuzhiyunCount device is as follows: 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties : 8*4882a593Smuzhiyun- compatible = "intel,lpc" 9*4882a593Smuzhiyun- intel,alt-gp-smi-enable : Enable SMI sources. This cell is written to the 10*4882a593Smuzhiyun ALT_GP_SMI_EN register 11*4882a593Smuzhiyun- intel,gen-dec : Specifies the values for the gen-dec registers. Up to four 12*4882a593Smuzhiyun cell pairs can be provided - the first of each pair is the base address and 13*4882a593Smuzhiyun the second is the size. These are written into the GENx_DEC registers of 14*4882a593Smuzhiyun the LPC device 15*4882a593Smuzhiyun- intel,gpi-routing : Specifies the GPI routing. There are 16 cells, valid 16*4882a593Smuzhiyun values are: 17*4882a593Smuzhiyun 0 No effect (default) 18*4882a593Smuzhiyun 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) 19*4882a593Smuzhiyun 2 SCI (if corresponding GPIO_EN bit is also set) 20*4882a593Smuzhiyun- intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H, 21*4882a593Smuzhiyun one cell for each. 22*4882a593Smuzhiyun 0x00 - 0000 = Reserved 23*4882a593Smuzhiyun 0x01 - 0001 = Reserved 24*4882a593Smuzhiyun 0x02 - 0010 = Reserved 25*4882a593Smuzhiyun 0x03 - 0011 = IRQ3 26*4882a593Smuzhiyun 0x04 - 0100 = IRQ4 27*4882a593Smuzhiyun 0x05 - 0101 = IRQ5 28*4882a593Smuzhiyun 0x06 - 0110 = IRQ6 29*4882a593Smuzhiyun 0x07 - 0111 = IRQ7 30*4882a593Smuzhiyun 0x08 - 1000 = Reserved 31*4882a593Smuzhiyun 0x09 - 1001 = IRQ9 32*4882a593Smuzhiyun 0x0A - 1010 = IRQ10 33*4882a593Smuzhiyun 0x0B - 1011 = IRQ11 34*4882a593Smuzhiyun 0x0C - 1100 = IRQ12 35*4882a593Smuzhiyun 0x0D - 1101 = Reserved 36*4882a593Smuzhiyun 0x0E - 1110 = IRQ14 37*4882a593Smuzhiyun 0x0F - 1111 = IRQ15 38*4882a593Smuzhiyun PIRQ[n]_ROUT[7] - PIRQ Routing Control 39*4882a593Smuzhiyun 0x80 - The PIRQ is not routed. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunExample 43*4882a593Smuzhiyun------- 44*4882a593Smuzhiyun 45*4882a593Smuzhiyunlpc { 46*4882a593Smuzhiyun compatible = "intel,lpc"; 47*4882a593Smuzhiyun #address-cells = <1>; 48*4882a593Smuzhiyun #size-cells = <1>; 49*4882a593Smuzhiyun intel,gen-dec = <0x800 0xfc 0x900 0xfc>; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b 52*4882a593Smuzhiyun 0x80 0x80 0x80 0x80>; 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * GPI routing 55*4882a593Smuzhiyun * 0 No effect (default) 56*4882a593Smuzhiyun * 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is 57*4882a593Smuzhiyun * also set) 58*4882a593Smuzhiyun * 2 SCI (if corresponding GPIO_EN bit is also set) 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun intel,gpi-routing = <0 0 0 0 0 0 0 2 61*4882a593Smuzhiyun 1 0 0 0 0 0 0 0>; 62*4882a593Smuzhiyun /* Enable EC SMI source */ 63*4882a593Smuzhiyun intel,alt-gp-smi-enable = <0x0100>; 64*4882a593Smuzhiyun}; 65