1*4882a593SmuzhiyunIntel Interrupt Router Device Binding 2*4882a593Smuzhiyun===================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe device tree node which describes the operation of the Intel Interrupt Router 5*4882a593Smuzhiyundevice is as follows: 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties : 8*4882a593Smuzhiyun- reg : Specifies the interrupt router's PCI configuration space address as 9*4882a593Smuzhiyun defined by the Open Firmware spec. 10*4882a593Smuzhiyun- compatible = "intel,irq-router" 11*4882a593Smuzhiyun- intel,pirq-config : Specifies the IRQ routing register programming mechanism. 12*4882a593Smuzhiyun Valid values are: 13*4882a593Smuzhiyun "pci": IRQ routing is controlled by PCI configuration registers 14*4882a593Smuzhiyun "ibase": IRQ routing is in the memory-mapped IBASE register block 15*4882a593Smuzhiyun- intel,ibase-offset : IBASE register offset in the interrupt router's PCI 16*4882a593Smuzhiyun configuration space, required only if intel,pirq-config = "ibase". 17*4882a593Smuzhiyun- intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must 18*4882a593Smuzhiyun be specified. The 8-bit ACTL register is seen on ICH series chipset, like 19*4882a593Smuzhiyun ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register. 20*4882a593Smuzhiyun- intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either 21*4882a593Smuzhiyun in the interrupt router's PCI configuration space, or IBASE. 22*4882a593Smuzhiyun- intel,pirq-link : Specifies the PIRQ link information with two cells. The 23*4882a593Smuzhiyun first cell is the register offset that controls the first PIRQ link routing. 24*4882a593Smuzhiyun The second cell is the total number of PIRQ links the router supports. 25*4882a593Smuzhiyun- intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the 26*4882a593Smuzhiyun 8259 PIC. Bit N is 1 means IRQ N is available to be routed. 27*4882a593Smuzhiyun- intel,pirq-routing : Specifies all PCI devices' IRQ routing information, 28*4882a593Smuzhiyun encoded as 3 cells a group for a device. The first cell is the device's PCI 29*4882a593Smuzhiyun bus number, device number and function number encoding with PCI_BDF() macro. 30*4882a593Smuzhiyun The second cell is the PCI interrupt pin used by this device. The last cell 31*4882a593Smuzhiyun is which PIRQ line the PCI interrupt pin is routed to. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunExample 35*4882a593Smuzhiyun------- 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun#include <dt-bindings/interrupt-router/intel-irq.h> 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun irq-router@1f,0 { 40*4882a593Smuzhiyun reg = <0x0000f800 0 0 0 0>; 41*4882a593Smuzhiyun compatible = "intel,irq-router"; 42*4882a593Smuzhiyun intel,pirq-config = "pci"; 43*4882a593Smuzhiyun intel,pirq-link = <0x60 8>; 44*4882a593Smuzhiyun intel,pirq-mask = <0xdef8>; 45*4882a593Smuzhiyun intel,pirq-routing = < 46*4882a593Smuzhiyun PCI_BDF(0, 2, 0) INTA PIRQA 47*4882a593Smuzhiyun PCI_BDF(0, 3, 0) INTA PIRQB 48*4882a593Smuzhiyun PCI_BDF(0, 8, 0) INTA PIRQC 49*4882a593Smuzhiyun PCI_BDF(0, 8, 1) INTB PIRQD 50*4882a593Smuzhiyun PCI_BDF(1, 6, 0) INTA PIRQE 51*4882a593Smuzhiyun PCI_BDF(1, 6, 1) INTB PIRQF 52*4882a593Smuzhiyun PCI_BDF(1, 6, 2) INTC PIRQG 53*4882a593Smuzhiyun PCI_BDF(1, 6, 3) INTD PIRQH 54*4882a593Smuzhiyun >; 55*4882a593Smuzhiyun }; 56