xref: /OK3568_Linux_fs/u-boot/doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunIntel x86 PINCTRL/GPIO controller
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunPin-muxing on broadwell devices can be described with a node for the PINCTRL
4*4882a593Smuzhiyunmaster node and a set of child nodes for each required pin state on the SoC.
5*4882a593SmuzhiyunThese pin states use phandles and are referred to but a configuration section
6*4882a593Smuzhiyunwhich lists all pins in the device.
7*4882a593Smuzhiyun
8*4882a593SmuzhiyunThe PINCTRL master node requires the following properties:
9*4882a593Smuzhiyun- compatible : "intel,x86-broadwell-pinctrl"
10*4882a593Smuzhiyun
11*4882a593SmuzhiyunPin state nodes must be sub-nodes of the pinctrl master node. The must have
12*4882a593Smuzhiyuna phandle. They can contain the following optional properties:
13*4882a593Smuzhiyun- mode-gpio	- forces the pin into GPIO mode
14*4882a593Smuzhiyun- output-value	- sets the default output value of the GPIO, 0 (low, default)
15*4882a593Smuzhiyun			or 1 (high)
16*4882a593Smuzhiyun- direction	- sets the direction of the gpio, either PIN_INPUT (default)
17*4882a593Smuzhiyun			or PIN_OUTPUT
18*4882a593Smuzhiyun- invert	- the input pin is inverted
19*4882a593Smuzhiyun- trigger	- sets the trigger type, either TRIGGER_EDGE (default) or
20*4882a593Smuzhiyun			TRIGGER_LEVEL
21*4882a593Smuzhiyun- sense-disable - the input state sense is disabled
22*4882a593Smuzhiyun- owner		0 sets the owner of the pin, either OWNER_ACPI (default) or
23*4882a593Smuzhiyun			ONWER_GPIO
24*4882a593Smuzhiyun- route		- sets whether the pin is routed, either PIRQ_APIC_MASK or
25*4882a593Smuzhiyun			PIRQ_APIC_ROUTE
26*4882a593Smuzhiyun- irq-enable	- the interrupt is enabled
27*4882a593Smuzhiyun- reset-rsmrst	- the pin will only be reset by RSMRST
28*4882a593Smuzhiyun- pirq-apic	- the pin will be routed to the IOxAPIC
29*4882a593Smuzhiyun
30*4882a593SmuzhiyunThe first pin state will be the default, so pins without a configuration will
31*4882a593Smuzhiyunuse that.
32*4882a593Smuzhiyun
33*4882a593SmuzhiyunThe pin configuration node is also a sub-node of the pinctrl master node, but
34*4882a593Smuzhiyundoes not have a phandle. It has a single property:
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun- config	- configuration to use for each pin. Each entry has of 3 cells:
37*4882a593Smuzhiyun			- GPIO number (0..94)
38*4882a593Smuzhiyun			- phandle of configuration (above)
39*4882a593Smuzhiyun			- interrupt number (0..15)
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun		  There should be one entry for each pin (i.e. 95 entries).
42*4882a593Smuzhiyun		  But missing pins will receive the default configuration.
43*4882a593Smuzhiyun
44*4882a593SmuzhiyunExample:
45*4882a593Smuzhiyun
46*4882a593Smuzhiyunpch_pinctrl {
47*4882a593Smuzhiyun	compatible = "intel,x86-broadwell-pinctrl";
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun	/* Put this first: it is the default */
50*4882a593Smuzhiyun	gpio_unused: gpio-unused {
51*4882a593Smuzhiyun		mode-gpio;
52*4882a593Smuzhiyun		direction = <PIN_INPUT>;
53*4882a593Smuzhiyun		owner = <OWNER_GPIO>;
54*4882a593Smuzhiyun		sense-disable;
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	gpio_acpi_sci: acpi-sci {
58*4882a593Smuzhiyun		mode-gpio;
59*4882a593Smuzhiyun		direction = <PIN_INPUT>;
60*4882a593Smuzhiyun		invert;
61*4882a593Smuzhiyun		route = <ROUTE_SCI>;
62*4882a593Smuzhiyun	};
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun	gpio_acpi_smi: acpi-smi {
65*4882a593Smuzhiyun		mode-gpio;
66*4882a593Smuzhiyun		direction = <PIN_INPUT>;
67*4882a593Smuzhiyun		invert;
68*4882a593Smuzhiyun		route = <ROUTE_SMI>;
69*4882a593Smuzhiyun	};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	gpio_input: gpio-input {
72*4882a593Smuzhiyun		mode-gpio;
73*4882a593Smuzhiyun		direction = <PIN_INPUT>;
74*4882a593Smuzhiyun		owner = <OWNER_GPIO>;
75*4882a593Smuzhiyun	};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun	gpio_input_invert: gpio-input-invert {
78*4882a593Smuzhiyun		mode-gpio;
79*4882a593Smuzhiyun		direction = <PIN_INPUT>;
80*4882a593Smuzhiyun		owner = <OWNER_GPIO>;
81*4882a593Smuzhiyun		invert;
82*4882a593Smuzhiyun	};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun	gpio_native: gpio-native {
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	gpio_out_high: gpio-out-high {
88*4882a593Smuzhiyun		mode-gpio;
89*4882a593Smuzhiyun		direction = <PIN_OUTPUT>;
90*4882a593Smuzhiyun		output-value = <1>;
91*4882a593Smuzhiyun		owner = <OWNER_GPIO>;
92*4882a593Smuzhiyun		sense-disable;
93*4882a593Smuzhiyun	};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun	gpio_out_low: gpio-out-low {
96*4882a593Smuzhiyun		mode-gpio;
97*4882a593Smuzhiyun		direction = <PIN_OUTPUT>;
98*4882a593Smuzhiyun		output-value = <0>;
99*4882a593Smuzhiyun		owner = <OWNER_GPIO>;
100*4882a593Smuzhiyun		sense-disable;
101*4882a593Smuzhiyun	};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun	gpio_pirq: gpio-pirq {
104*4882a593Smuzhiyun		mode-gpio;
105*4882a593Smuzhiyun		direction = <PIN_INPUT>;
106*4882a593Smuzhiyun		owner = <OWNER_GPIO>;
107*4882a593Smuzhiyun		pirq-apic = <PIRQ_APIC_ROUTE>;
108*4882a593Smuzhiyun	};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun	soc_gpio@0 {
111*4882a593Smuzhiyun		config =
112*4882a593Smuzhiyun			<0 &gpio_unused 0>,	/* unused */
113*4882a593Smuzhiyun			<1 &gpio_unused 0>,	/* unused */
114*4882a593Smuzhiyun			<2 &gpio_unused 0>,	/* unused */
115*4882a593Smuzhiyun			<3 &gpio_unused 0>,	/* unused */
116*4882a593Smuzhiyun			<4 &gpio_native 0>,	/* native: i2c0_sda_gpio4 */
117*4882a593Smuzhiyun			<5 &gpio_native 0>,	/* native: i2c0_scl_gpio5 */
118*4882a593Smuzhiyun			<6 &gpio_native 0>,	/* native: i2c1_sda_gpio6 */
119*4882a593Smuzhiyun			<7 &gpio_native 0>,	/* native: i2c1_scl_gpio7 */
120*4882a593Smuzhiyun			<8 &gpio_acpi_sci 0>,	/* pch_lte_wake_l */
121*4882a593Smuzhiyun			<9 &gpio_input_invert 0>,/* trackpad_int_l (wake) */
122*4882a593Smuzhiyun			<10 &gpio_acpi_sci 0>,	/* pch_wlan_wake_l */
123*4882a593Smuzhiyun			<11 &gpio_unused 0>,	/* unused */
124*4882a593Smuzhiyun			<12 &gpio_unused 0>,	/* unused */
125*4882a593Smuzhiyun			<13 &gpio_pirq 3>,	/* trackpad_int_l (pirql) */
126*4882a593Smuzhiyun			<14 &gpio_pirq 4>,	/* touch_int_l (pirqm) */
127*4882a593Smuzhiyun			<15 &gpio_unused 0>,	/* unused (strap) */
128*4882a593Smuzhiyun			<16 &gpio_input 0>,	/* pch_wp */
129*4882a593Smuzhiyun			<17 &gpio_unused 0>,	/* unused */
130*4882a593Smuzhiyun			<18 &gpio_unused 0>,	/* unused */
131*4882a593Smuzhiyun			<19 &gpio_unused 0>,	/* unused */
132*4882a593Smuzhiyun			<20 &gpio_native 0>,	/* pcie_wlan_clkreq_l */
133*4882a593Smuzhiyun			<21 &gpio_out_high 0>,	/* pp3300_ssd_en */
134*4882a593Smuzhiyun			<22 &gpio_unused 0>,	/* unused */
135*4882a593Smuzhiyun			<23 &gpio_out_low 0>,	/* pp3300_autobahn_en */
136*4882a593Smuzhiyun			<24 &gpio_unused 0>,	/* unused */
137*4882a593Smuzhiyun			<25 &gpio_input 0>,	/* ec_in_rw */
138*4882a593Smuzhiyun			<26 &gpio_unused 0>,	/* unused */
139*4882a593Smuzhiyun			<27 &gpio_acpi_sci 0>,	/* pch_wake_l */
140*4882a593Smuzhiyun			<28 &gpio_unused 0>,	/* unused */
141*4882a593Smuzhiyun			<29 &gpio_unused 0>,	/* unused */
142*4882a593Smuzhiyun			<30 &gpio_native 0>,	/* native: pch_suswarn_l */
143*4882a593Smuzhiyun			<31 &gpio_native 0>,	/* native: acok_buf */
144*4882a593Smuzhiyun			<32 &gpio_native 0>,	/* native: lpc_clkrun_l */
145*4882a593Smuzhiyun			<33 &gpio_native 0>,	/* native: ssd_devslp */
146*4882a593Smuzhiyun			<34 &gpio_acpi_smi 0>,	/* ec_smi_l */
147*4882a593Smuzhiyun			<35 &gpio_acpi_smi 0>,	/* pch_nmi_dbg_l (route in nmi_en) */
148*4882a593Smuzhiyun			<36 &gpio_acpi_sci 0>,	/* ec_sci_l */
149*4882a593Smuzhiyun			<37 &gpio_unused 0>,	/* unused */
150*4882a593Smuzhiyun			<38 &gpio_unused 0>,	/* unused */
151*4882a593Smuzhiyun			<39 &gpio_unused 0>,	/* unused */
152*4882a593Smuzhiyun			<40 &gpio_native 0>,	/* native: pch_usb1_oc_l */
153*4882a593Smuzhiyun			<41 &gpio_native 0>,	/* native: pch_usb2_oc_l */
154*4882a593Smuzhiyun			<42 &gpio_unused 0>,	/* wlan_disable_l */
155*4882a593Smuzhiyun			<43 &gpio_out_high 0>,	/* pp1800_codec_en */
156*4882a593Smuzhiyun			<44 &gpio_unused 0>,	/* unused */
157*4882a593Smuzhiyun			<45 &gpio_acpi_sci 0>,	/* dsp_int - codec wake */
158*4882a593Smuzhiyun			<46 &gpio_pirq 6>,	/* hotword_det_l_3v3 (pirqo) - codec irq */
159*4882a593Smuzhiyun			<47 &gpio_out_low 0>,	/* ssd_reset_l */
160*4882a593Smuzhiyun			<48 &gpio_unused 0>,	/* unused */
161*4882a593Smuzhiyun			<49 &gpio_unused 0>,	/* unused */
162*4882a593Smuzhiyun			<50 &gpio_unused 0>,	/* unused */
163*4882a593Smuzhiyun			<51 &gpio_unused 0>,	/* unused */
164*4882a593Smuzhiyun			<52 &gpio_input 0>,	/* sim_det */
165*4882a593Smuzhiyun			<53 &gpio_unused 0>,	/* unused */
166*4882a593Smuzhiyun			<54 &gpio_unused 0>,	/* unused */
167*4882a593Smuzhiyun			<55 &gpio_unused 0>,	/* unused */
168*4882a593Smuzhiyun			<56 &gpio_unused 0>,	/* unused */
169*4882a593Smuzhiyun			<57 &gpio_out_high 0>,	/* codec_reset_l */
170*4882a593Smuzhiyun			<58 &gpio_unused 0>,	/* unused */
171*4882a593Smuzhiyun			<59 &gpio_out_high 0>,	/* lte_disable_l */
172*4882a593Smuzhiyun			<60 &gpio_unused 0>,	/* unused */
173*4882a593Smuzhiyun			<61 &gpio_native 0>,	/* native: pch_sus_stat */
174*4882a593Smuzhiyun			<62 &gpio_native 0>,	/* native: pch_susclk */
175*4882a593Smuzhiyun			<63 &gpio_native 0>,	/* native: pch_slp_s5_l */
176*4882a593Smuzhiyun			<64 &gpio_unused 0>,	/* unused */
177*4882a593Smuzhiyun			<65 &gpio_input 0>,	/* ram_id3 */
178*4882a593Smuzhiyun			<66 &gpio_input 0>,	/* ram_id3_old (strap) */
179*4882a593Smuzhiyun			<67 &gpio_input 0>,	/* ram_id0 */
180*4882a593Smuzhiyun			<68 &gpio_input 0>,	/* ram_id1 */
181*4882a593Smuzhiyun			<69 &gpio_input 0>,	/* ram_id2 */
182*4882a593Smuzhiyun			<70 &gpio_unused 0>,	/* unused */
183*4882a593Smuzhiyun			<71 &gpio_native 0>,	/* native: modphy_en */
184*4882a593Smuzhiyun			<72 &gpio_unused 0>,	/* unused */
185*4882a593Smuzhiyun			<73 &gpio_unused 0>,	/* unused */
186*4882a593Smuzhiyun			<74 &gpio_unused 0>,	/* unused */
187*4882a593Smuzhiyun			<75 &gpio_unused 0>,	/* unused */
188*4882a593Smuzhiyun			<76 &gpio_unused 0>,	/* unused */
189*4882a593Smuzhiyun			<77 &gpio_unused 0>,	/* unused */
190*4882a593Smuzhiyun			<78 &gpio_unused 0>,	/* unused */
191*4882a593Smuzhiyun			<79 &gpio_unused 0>,	/* unused */
192*4882a593Smuzhiyun			<80 &gpio_unused 0>,	/* unused */
193*4882a593Smuzhiyun			<81 &gpio_unused 0>,	/* unused */
194*4882a593Smuzhiyun			<82 &gpio_native 0>,	/* native: ec_rcin_l */
195*4882a593Smuzhiyun			<83 &gpio_native 0>,	/* gspi0_cs */
196*4882a593Smuzhiyun			<84 &gpio_native 0>,	/* gspi0_clk */
197*4882a593Smuzhiyun			<85 &gpio_native 0>,	/* gspi0_miso */
198*4882a593Smuzhiyun			<86 &gpio_native 0>,	/* gspi0_mosi (strap) */
199*4882a593Smuzhiyun			<87 &gpio_unused 0>,	/* unused */
200*4882a593Smuzhiyun			<88 &gpio_unused 0>,	/* unused */
201*4882a593Smuzhiyun			<89 &gpio_out_high 0>,	/* pp3300_sd_en */
202*4882a593Smuzhiyun			<90 &gpio_unused 0>,	/* unused */
203*4882a593Smuzhiyun			<91 &gpio_unused 0>,	/* unused */
204*4882a593Smuzhiyun			<92 &gpio_unused 0>,	/* unused */
205*4882a593Smuzhiyun			<93 &gpio_unused 0>,	/* unused */
206*4882a593Smuzhiyun			<94 &gpio_unused 0 >;	/* unused */
207*4882a593Smuzhiyun	};
208*4882a593Smuzhiyun};
209