1*4882a593SmuzhiyunIntel x86 PINCTRL/GPIO controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunPin-muxing on x86 can be described with a node for the PINCTRL master 4*4882a593Smuzhiyunnode and a set of child nodes for each pin on the SoC. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThe PINCTRL master node requires the following properties: 7*4882a593Smuzhiyun- compatible : "intel,x86-pinctrl" 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunPin nodes must be children of the pinctrl master node and can 10*4882a593Smuzhiyuncontain the following properties: 11*4882a593Smuzhiyun- pad-offset - (required) offset in the IOBASE for the pin to configure 12*4882a593Smuzhiyun- gpio-offset - (required only when 'mode-gpio' is set) 2 cells 13*4882a593Smuzhiyun - offset in the GPIOBASE for the pin to configure 14*4882a593Smuzhiyun - the bit shift in this register (4 = bit 4) 15*4882a593Smuzhiyun- mode-gpio - (optional) standalone property to force the pin into GPIO mode 16*4882a593Smuzhiyun- mode-func - (optional) function number to assign to the pin. If 17*4882a593Smuzhiyun 'mode-gpio' is set, this property will be ignored. 18*4882a593Smuzhiyunin case of 'mode-gpio' property set: 19*4882a593Smuzhiyun- output-value - (optional) this set the default output value of the GPIO 20*4882a593Smuzhiyun- direction - (optional) this set the direction of the gpio 21*4882a593Smuzhiyun- pull-strength - (optional) this set the pull strength of the pin 22*4882a593Smuzhiyun- pull-assign - (optional) this set the pull assignement (up/down) of the pin 23*4882a593Smuzhiyun- invert - (optional) this input pin is inverted 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunpin_usb_host_en0@0 { 28*4882a593Smuzhiyun gpio-offset = <0x80 8>; 29*4882a593Smuzhiyun pad-offset = <0x260>; 30*4882a593Smuzhiyun mode-gpio; 31*4882a593Smuzhiyun output-value = <1>; 32*4882a593Smuzhiyun direction = <PIN_OUTPUT>; 33*4882a593Smuzhiyun}; 34