xref: /OK3568_Linux_fs/u-boot/doc/device-tree-bindings/gpio/gpio.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunSpecifying GPIO information for devices
2*4882a593Smuzhiyun============================================
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun1) gpios property
5*4882a593Smuzhiyun-----------------
6*4882a593Smuzhiyun
7*4882a593SmuzhiyunNodes that makes use of GPIOs should specify them using one or more
8*4882a593Smuzhiyunproperties, each containing a 'gpio-list':
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun	gpio-list ::= <single-gpio> [gpio-list]
11*4882a593Smuzhiyun	single-gpio ::= <gpio-phandle> <gpio-specifier>
12*4882a593Smuzhiyun	gpio-phandle : phandle to gpio controller node
13*4882a593Smuzhiyun	gpio-specifier : Array of #gpio-cells specifying specific gpio
14*4882a593Smuzhiyun			 (controller specific)
15*4882a593Smuzhiyun
16*4882a593SmuzhiyunGPIO properties should be named "[<name>-]gpios", with <name> being the purpose
17*4882a593Smuzhiyunof this GPIO for the device. While a non-existent <name> is considered valid
18*4882a593Smuzhiyunfor compatibility reasons (resolving to the "gpios" property), it is not allowed
19*4882a593Smuzhiyunfor new bindings.
20*4882a593Smuzhiyun
21*4882a593SmuzhiyunGPIO properties can contain one or more GPIO phandles, but only in exceptional
22*4882a593Smuzhiyuncases should they contain more than one. If your device uses several GPIOs with
23*4882a593Smuzhiyundistinct functions, reference each of them under its own property, giving it a
24*4882a593Smuzhiyunmeaningful name. The only case where an array of GPIOs is accepted is when
25*4882a593Smuzhiyunseveral GPIOs serve the same function (e.g. a parallel data line).
26*4882a593Smuzhiyun
27*4882a593SmuzhiyunThe exact purpose of each gpios property must be documented in the device tree
28*4882a593Smuzhiyunbinding of the device.
29*4882a593Smuzhiyun
30*4882a593SmuzhiyunThe following example could be used to describe GPIO pins used as device enable
31*4882a593Smuzhiyunand bit-banged data signals:
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	gpio1: gpio1 {
34*4882a593Smuzhiyun		gpio-controller
35*4882a593Smuzhiyun		 #gpio-cells = <2>;
36*4882a593Smuzhiyun	};
37*4882a593Smuzhiyun	gpio2: gpio2 {
38*4882a593Smuzhiyun		gpio-controller
39*4882a593Smuzhiyun		 #gpio-cells = <1>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun	[...]
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun	enable-gpios = <&gpio2 2>;
44*4882a593Smuzhiyun	data-gpios = <&gpio1 12 0>,
45*4882a593Smuzhiyun		     <&gpio1 13 0>,
46*4882a593Smuzhiyun		     <&gpio1 14 0>,
47*4882a593Smuzhiyun		     <&gpio1 15 0>;
48*4882a593Smuzhiyun
49*4882a593SmuzhiyunNote that gpio-specifier length is controller dependent.  In the
50*4882a593Smuzhiyunabove example, &gpio1 uses 2 cells to specify a gpio, while &gpio2
51*4882a593Smuzhiyunonly uses one.
52*4882a593Smuzhiyun
53*4882a593Smuzhiyungpio-specifier may encode: bank, pin position inside the bank,
54*4882a593Smuzhiyunwhether pin is open-drain and whether pin is logically inverted.
55*4882a593SmuzhiyunExact meaning of each specifier cell is controller specific, and must
56*4882a593Smuzhiyunbe documented in the device tree binding for the device. Use the macros
57*4882a593Smuzhiyundefined in include/dt-bindings/gpio/gpio.h whenever possible:
58*4882a593Smuzhiyun
59*4882a593SmuzhiyunExample of a node using GPIOs:
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun	node {
62*4882a593Smuzhiyun		enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>;
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun
65*4882a593SmuzhiyunGPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes
66*4882a593SmuzhiyunGPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun1.1) GPIO specifier best practices
69*4882a593Smuzhiyun----------------------------------
70*4882a593Smuzhiyun
71*4882a593SmuzhiyunA gpio-specifier should contain a flag indicating the GPIO polarity; active-
72*4882a593Smuzhiyunhigh or active-low. If it does, the following best practices should be
73*4882a593Smuzhiyunfollowed:
74*4882a593Smuzhiyun
75*4882a593SmuzhiyunThe gpio-specifier's polarity flag should represent the physical level at the
76*4882a593SmuzhiyunGPIO controller that achieves (or represents, for inputs) a logically asserted
77*4882a593Smuzhiyunvalue at the device. The exact definition of logically asserted should be
78*4882a593Smuzhiyundefined by the binding for the device. If the board inverts the signal between
79*4882a593Smuzhiyunthe GPIO controller and the device, then the gpio-specifier will represent the
80*4882a593Smuzhiyunopposite physical level than the signal at the device's pin.
81*4882a593Smuzhiyun
82*4882a593SmuzhiyunWhen the device's signal polarity is configurable, the binding for the
83*4882a593Smuzhiyundevice must either:
84*4882a593Smuzhiyun
85*4882a593Smuzhiyuna) Define a single static polarity for the signal, with the expectation that
86*4882a593Smuzhiyunany software using that binding would statically program the device to use
87*4882a593Smuzhiyunthat signal polarity.
88*4882a593Smuzhiyun
89*4882a593SmuzhiyunThe static choice of polarity may be either:
90*4882a593Smuzhiyun
91*4882a593Smuzhiyuna1) (Preferred) Dictated by a binding-specific DT property.
92*4882a593Smuzhiyun
93*4882a593Smuzhiyunor:
94*4882a593Smuzhiyun
95*4882a593Smuzhiyuna2) Defined statically by the DT binding itself.
96*4882a593Smuzhiyun
97*4882a593SmuzhiyunIn particular, the polarity cannot be derived from the gpio-specifier, since
98*4882a593Smuzhiyunthat would prevent the DT from separately representing the two orthogonal
99*4882a593Smuzhiyunconcepts of configurable signal polarity in the device, and possible board-
100*4882a593Smuzhiyunlevel signal inversion.
101*4882a593Smuzhiyun
102*4882a593Smuzhiyunor:
103*4882a593Smuzhiyun
104*4882a593Smuzhiyunb) Pick a single option for device signal polarity, and document this choice
105*4882a593Smuzhiyunin the binding. The gpio-specifier should represent the polarity of the signal
106*4882a593Smuzhiyun(at the GPIO controller) assuming that the device is configured for this
107*4882a593Smuzhiyunparticular signal polarity choice. If software chooses to program the device
108*4882a593Smuzhiyunto generate or receive a signal of the opposite polarity, software will be
109*4882a593Smuzhiyunresponsible for correctly interpreting (inverting) the GPIO signal at the GPIO
110*4882a593Smuzhiyuncontroller.
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun2) gpio-controller nodes
113*4882a593Smuzhiyun------------------------
114*4882a593Smuzhiyun
115*4882a593SmuzhiyunEvery GPIO controller node must contain both an empty "gpio-controller"
116*4882a593Smuzhiyunproperty, and a #gpio-cells integer property, which indicates the number of
117*4882a593Smuzhiyuncells in a gpio-specifier.
118*4882a593Smuzhiyun
119*4882a593SmuzhiyunExample of two SOC GPIO banks defined as gpio-controller nodes:
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun	qe_pio_a: gpio-controller@1400 {
122*4882a593Smuzhiyun		compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
123*4882a593Smuzhiyun		reg = <0x1400 0x18>;
124*4882a593Smuzhiyun		gpio-controller;
125*4882a593Smuzhiyun		#gpio-cells = <2>;
126*4882a593Smuzhiyun	};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun	qe_pio_e: gpio-controller@1460 {
129*4882a593Smuzhiyun		compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
130*4882a593Smuzhiyun		reg = <0x1460 0x18>;
131*4882a593Smuzhiyun		gpio-controller;
132*4882a593Smuzhiyun		#gpio-cells = <2>;
133*4882a593Smuzhiyun	};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun2.1) gpio- and pin-controller interaction
136*4882a593Smuzhiyun-----------------------------------------
137*4882a593Smuzhiyun
138*4882a593SmuzhiyunSome or all of the GPIOs provided by a GPIO controller may be routed to pins
139*4882a593Smuzhiyunon the package via a pin controller. This allows muxing those pins between
140*4882a593SmuzhiyunGPIO and other functions.
141*4882a593Smuzhiyun
142*4882a593SmuzhiyunIt is useful to represent which GPIOs correspond to which pins on which pin
143*4882a593Smuzhiyuncontrollers. The gpio-ranges property described below represents this, and
144*4882a593Smuzhiyuncontains information structures as follows:
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun	gpio-range-list ::= <single-gpio-range> [gpio-range-list]
147*4882a593Smuzhiyun	single-gpio-range ::= <numeric-gpio-range> | <named-gpio-range>
148*4882a593Smuzhiyun	numeric-gpio-range ::=
149*4882a593Smuzhiyun			<pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
150*4882a593Smuzhiyun	named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'
151*4882a593Smuzhiyun	pinctrl-phandle : phandle to pin controller node
152*4882a593Smuzhiyun	gpio-base : Base GPIO ID in the GPIO controller
153*4882a593Smuzhiyun	pinctrl-base : Base pinctrl pin ID in the pin controller
154*4882a593Smuzhiyun	count : The number of GPIOs/pins in this range
155*4882a593Smuzhiyun
156*4882a593SmuzhiyunThe "pin controller node" mentioned above must conform to the bindings
157*4882a593Smuzhiyundescribed in ../pinctrl/pinctrl-bindings.txt.
158*4882a593Smuzhiyun
159*4882a593SmuzhiyunIn case named gpio ranges are used (ranges with both <pinctrl-base> and
160*4882a593Smuzhiyun<count> set to 0), the property gpio-ranges-group-names contains one string
161*4882a593Smuzhiyunfor every single-gpio-range in gpio-ranges:
162*4882a593Smuzhiyun	gpiorange-names-list ::= <gpiorange-name> [gpiorange-names-list]
163*4882a593Smuzhiyun	gpiorange-name : Name of the pingroup associated to the GPIO range in
164*4882a593Smuzhiyun			the respective pin controller.
165*4882a593Smuzhiyun
166*4882a593SmuzhiyunElements of gpiorange-names-list corresponding to numeric ranges contain
167*4882a593Smuzhiyunthe empty string. Elements of gpiorange-names-list corresponding to named
168*4882a593Smuzhiyunranges contain the name of a pin group defined in the respective pin
169*4882a593Smuzhiyuncontroller. The number of pins/GPIOs in the range is the number of pins in
170*4882a593Smuzhiyunthat pin group.
171*4882a593Smuzhiyun
172*4882a593SmuzhiyunPrevious versions of this binding required all pin controller nodes that
173*4882a593Smuzhiyunwere referenced by any gpio-ranges property to contain a property named
174*4882a593Smuzhiyun#gpio-range-cells with value <3>. This requirement is now deprecated.
175*4882a593SmuzhiyunHowever, that property may still exist in older device trees for
176*4882a593Smuzhiyuncompatibility reasons, and would still be required even in new device
177*4882a593Smuzhiyuntrees that need to be compatible with older software.
178*4882a593Smuzhiyun
179*4882a593SmuzhiyunExample 1:
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun	qe_pio_e: gpio-controller@1460 {
182*4882a593Smuzhiyun		#gpio-cells = <2>;
183*4882a593Smuzhiyun		compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
184*4882a593Smuzhiyun		reg = <0x1460 0x18>;
185*4882a593Smuzhiyun		gpio-controller;
186*4882a593Smuzhiyun		gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun
189*4882a593SmuzhiyunHere, a single GPIO controller has GPIOs 0..9 routed to pin controller
190*4882a593Smuzhiyunpinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's
191*4882a593Smuzhiyunpins 50..59.
192*4882a593Smuzhiyun
193*4882a593SmuzhiyunExample 2:
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun	gpio_pio_i: gpio-controller@14B0 {
196*4882a593Smuzhiyun		#gpio-cells = <2>;
197*4882a593Smuzhiyun		compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
198*4882a593Smuzhiyun		reg = <0x1480 0x18>;
199*4882a593Smuzhiyun		gpio-controller;
200*4882a593Smuzhiyun		gpio-ranges =			<&pinctrl1 0 20 10>,
201*4882a593Smuzhiyun						<&pinctrl2 10 0 0>,
202*4882a593Smuzhiyun						<&pinctrl1 15 0 10>,
203*4882a593Smuzhiyun						<&pinctrl2 25 0 0>;
204*4882a593Smuzhiyun		gpio-ranges-group-names =	"",
205*4882a593Smuzhiyun						"foo",
206*4882a593Smuzhiyun						"",
207*4882a593Smuzhiyun						"bar";
208*4882a593Smuzhiyun	};
209*4882a593Smuzhiyun
210*4882a593SmuzhiyunHere, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO
211*4882a593Smuzhiyunranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2
212*4882a593Smuzhiyunare named "foo" and "bar".
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun3) GPIO hog definitions
215*4882a593Smuzhiyun-----------------------
216*4882a593Smuzhiyun
217*4882a593SmuzhiyunThe GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
218*4882a593Smuzhiyunproviding automatic GPIO request and configuration as part of the
219*4882a593Smuzhiyungpio-controller's driver probe function.
220*4882a593Smuzhiyun
221*4882a593SmuzhiyunEach GPIO hog definition is represented as a child node of the GPIO controller.
222*4882a593SmuzhiyunRequired properties:
223*4882a593Smuzhiyun- gpio-hog:   A property specifying that this child node represents a GPIO hog.
224*4882a593Smuzhiyun- gpios:      Store the GPIO information (id, flags) for the GPIO to
225*4882a593Smuzhiyun	      affect.
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun              ! Not yet support more than one gpio !
228*4882a593Smuzhiyun
229*4882a593SmuzhiyunOnly one of the following properties scanned in the order shown below.
230*4882a593Smuzhiyun- input:      A property specifying to set the GPIO direction as input.
231*4882a593Smuzhiyun- output-low  A property specifying to set the GPIO direction as output with
232*4882a593Smuzhiyun	      the value low.
233*4882a593Smuzhiyun- output-high A property specifying to set the GPIO direction as output with
234*4882a593Smuzhiyun	      the value high.
235*4882a593Smuzhiyun
236*4882a593SmuzhiyunOptional properties:
237*4882a593Smuzhiyun- line-name:  The GPIO label name. If not present the node name is used.
238*4882a593Smuzhiyun
239*4882a593SmuzhiyunExample:
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun        tca6416@20 {
242*4882a593Smuzhiyun                compatible = "ti,tca6416";
243*4882a593Smuzhiyun                reg = <0x20>;
244*4882a593Smuzhiyun                #gpio-cells = <2>;
245*4882a593Smuzhiyun                gpio-controller;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun                env_reset {
248*4882a593Smuzhiyun                        gpio-hog;
249*4882a593Smuzhiyun                        input;
250*4882a593Smuzhiyun                        gpios = <6 GPIO_ACTIVE_LOW>;
251*4882a593Smuzhiyun                };
252*4882a593Smuzhiyun                boot_rescue {
253*4882a593Smuzhiyun                        gpio-hog;
254*4882a593Smuzhiyun                        input;
255*4882a593Smuzhiyun                        line-name = "foo-bar-gpio";
256*4882a593Smuzhiyun                        gpios = <7 GPIO_ACTIVE_LOW>;
257*4882a593Smuzhiyun                };
258*4882a593Smuzhiyun        };
259*4882a593Smuzhiyun
260*4882a593SmuzhiyunFor the above Example you can than access the gpio in your boardcode
261*4882a593Smuzhiyunwith:
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun	struct gpio_desc *desc;
264*4882a593Smuzhiyun	int ret;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun	ret = gpio_hog_lookup_name("boot_rescue", &desc);
267*4882a593Smuzhiyun	if (ret)
268*4882a593Smuzhiyun		return;
269*4882a593Smuzhiyun	if (dm_gpio_get_value(desc) == 1)
270*4882a593Smuzhiyun		printf("\nBooting into Rescue System\n");
271*4882a593Smuzhiyun	else if (dm_gpio_get_value(desc) == 0)
272*4882a593Smuzhiyun		printf("\nBoot normal\n");
273