1*4882a593SmuzhiyunRK3368 dynamic memory controller driver 2*4882a593Smuzhiyun======================================= 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe RK3368 DMC (dynamic memory controller) driver supports setup/initialisation 5*4882a593Smuzhiyunduring TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on 6*4882a593Smuzhiyunthe following key configuration data: 7*4882a593Smuzhiyun (a) a target-frequency (i.e. operating point) for the memory operation 8*4882a593Smuzhiyun (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware 9*4882a593Smuzhiyun (c) a memory-schedule (i.e. mapping from physical addresses to the address 10*4882a593Smuzhiyun pins of the memory bus) 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunRequired properties 13*4882a593Smuzhiyun------------------- 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- compatible: "rockchip,rk3368-dmc" 16*4882a593Smuzhiyun- reg 17*4882a593Smuzhiyun protocol controller (PCTL) address and PHY controller (DDRPHY) address 18*4882a593Smuzhiyun- rockchip,ddr-speed-bin 19*4882a593Smuzhiyun the DDR3 device's speed-bin (as specified according to JESD-79) 20*4882a593Smuzhiyun DDR3_800D (5-5-5) 21*4882a593Smuzhiyun DDR3_800E (6-6-6) 22*4882a593Smuzhiyun DDR3_1066E (6-6-6) 23*4882a593Smuzhiyun DDR3_1066F (7-7-7) 24*4882a593Smuzhiyun DDR3_1066G (8-8-8) 25*4882a593Smuzhiyun DDR3_1333F (7-7-7) 26*4882a593Smuzhiyun DDR3_1333G (8-8-8) 27*4882a593Smuzhiyun DDR3_1333H (9-9-9) 28*4882a593Smuzhiyun DDR3_1333J (10-10-10) 29*4882a593Smuzhiyun DDR3_1600G (8-8-8) 30*4882a593Smuzhiyun DDR3_1600H (9-9-9) 31*4882a593Smuzhiyun DDR3_1600J (10-10-10) 32*4882a593Smuzhiyun DDR3_1600K (11-11-11) 33*4882a593Smuzhiyun DDR3_1866J (10-10-10) 34*4882a593Smuzhiyun DDR3_1866K (11-11-11) 35*4882a593Smuzhiyun DDR3_1866L (12-12-12) 36*4882a593Smuzhiyun DDR3_1866M (13-13-13) 37*4882a593Smuzhiyun DDR3_2133K (11-11-11) 38*4882a593Smuzhiyun DDR3_2133L (12-12-12) 39*4882a593Smuzhiyun DDR3_2133M (13-13-13) 40*4882a593Smuzhiyun DDR3_2133N (14-14-14) 41*4882a593Smuzhiyun- rockchip,ddr-frequency: 42*4882a593Smuzhiyun target DDR clock frequency in Hz (not all frequencies may be supported, 43*4882a593Smuzhiyun as there's some cooperation from the clock-driver required) 44*4882a593Smuzhiyun- rockchip,memory-schedule: 45*4882a593Smuzhiyun controls the decoding of physical addresses to DRAM addressing (i.e. how 46*4882a593Smuzhiyun the physical address maps onto the address pins/chip-select of the device) 47*4882a593Smuzhiyun DMC_MSCH_CBDR: column -> bank -> device -> row 48*4882a593Smuzhiyun DMC_MSCH_CBRD: column -> band -> row -> device 49*4882a593Smuzhiyun DMC_MSCH_CRBD: column -> row -> band -> device 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunExample (for DDR3-1600K and 800MHz) 52*4882a593Smuzhiyun----------------------------------- 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #include <dt-bindings/memory/rk3368-dmc.h> 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun dmc: dmc@ff610000 { 57*4882a593Smuzhiyun u-boot,dm-pre-reloc; 58*4882a593Smuzhiyun compatible = "rockchip,rk3368-dmc"; 59*4882a593Smuzhiyun reg = <0 0xff610000 0 0x400 60*4882a593Smuzhiyun 0 0xff620000 0 0x400>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun &dmc { 64*4882a593Smuzhiyun rockchip,ddr-speed-bin = <DDR3_1600K>; 65*4882a593Smuzhiyun rockchip,ddr-frequency = <800000000>; 66*4882a593Smuzhiyun rockchip,memory-schedule = <DMC_MSCH_CBRD>; 67*4882a593Smuzhiyun }; 68