1*4882a593Smuzhiyun* Rockchip RK3188/RK3066 Clock and Reset Unit 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe RK3188/RK3066 clock controller generates and supplies clock to various 4*4882a593Smuzhiyuncontrollers within the SoC and also implements a reset controller for SoC 5*4882a593Smuzhiyunperipherals. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired Properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or 10*4882a593Smuzhiyun "rockchip,rk3066a-cru" 11*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 12*4882a593Smuzhiyun region. 13*4882a593Smuzhiyun- #clock-cells: should be 1. 14*4882a593Smuzhiyun- #reset-cells: should be 1. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunOptional Properties: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- rockchip,grf: phandle to the syscon managing the "general register files" 19*4882a593Smuzhiyun If missing pll rates are not changable, due to the missing pll lock status. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunEach clock is assigned an identifier and client nodes can use this identifier 22*4882a593Smuzhiyunto specify the clock which they consume. All available clocks are defined as 23*4882a593Smuzhiyunpreprocessor macros in the dt-bindings/clock/rk3188-cru.h and 24*4882a593Smuzhiyundt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. 25*4882a593SmuzhiyunSimilar macros exist for the reset sources in these files. 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunExternal clocks: 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunThere are several clocks that are generated outside the SoC. It is expected 30*4882a593Smuzhiyunthat they are defined using standard clock bindings with following 31*4882a593Smuzhiyunclock-output-names: 32*4882a593Smuzhiyun - "xin24m" - crystal input - required, 33*4882a593Smuzhiyun - "xin32k" - rtc clock - optional, 34*4882a593Smuzhiyun - "xin27m" - 27mhz crystal input on rk3066 - optional, 35*4882a593Smuzhiyun - "ext_hsadc" - external HSADC clock - optional, 36*4882a593Smuzhiyun - "ext_cif0" - external camera clock - optional, 37*4882a593Smuzhiyun - "ext_rmii" - external RMII clock - optional, 38*4882a593Smuzhiyun - "ext_jtag" - externalJTAG clock - optional 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample: Clock controller node: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun cru: cru@20000000 { 43*4882a593Smuzhiyun compatible = "rockchip,rk3188-cru"; 44*4882a593Smuzhiyun reg = <0x20000000 0x1000>; 45*4882a593Smuzhiyun rockchip,grf = <&grf>; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #clock-cells = <1>; 48*4882a593Smuzhiyun #reset-cells = <1>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunExample: UART controller node that consumes the clock generated by the clock 52*4882a593Smuzhiyun controller: 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun uart0: serial@10124000 { 55*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 56*4882a593Smuzhiyun reg = <0x10124000 0x400>; 57*4882a593Smuzhiyun interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 58*4882a593Smuzhiyun reg-shift = <2>; 59*4882a593Smuzhiyun reg-io-width = <1>; 60*4882a593Smuzhiyun clocks = <&cru SCLK_UART0>; 61*4882a593Smuzhiyun }; 62