1*4882a593SmuzhiyunRockchip Dynamic Memory Controller Driver 2*4882a593SmuzhiyunRequired properties: 3*4882a593Smuzhiyun- compatible: "rockchip,rk3399-dmc", "syscon" 4*4882a593Smuzhiyun- rockchip,cru: this driver should access cru regs, so need get cru here 5*4882a593Smuzhiyun- rockchip,pmucru: this driver should access pmucru regs, so need get pmucru here 6*4882a593Smuzhiyun- rockchip,pmugrf: this driver should access pmugrf regs, so need get pmugrf here 7*4882a593Smuzhiyun- rockchip,pmusgrf: this driver should access pmusgrf regs, so need get pmusgrf here 8*4882a593Smuzhiyun- rockchip,cic: this driver should access cic regs, so need get cic here 9*4882a593Smuzhiyun- reg: dynamic ram protocol controller(PCTL) address, PHY Independent(PI) address, phy controller(PHYCTL) address and memory schedule(MSCH) address 10*4882a593Smuzhiyun- clock: must include clock specifiers corresponding to entries in the clock-names property. 11*4882a593Smuzhiyun Must contain 12*4882a593Smuzhiyun dmc_clk: for ddr working frequency 13*4882a593Smuzhiyun- rockchip,sdram-params: SDRAM parameters, including all the information by ddr driver: 14*4882a593Smuzhiyun Must contain 15*4882a593Smuzhiyun Genarate by vendor tool and adjust for U-Boot dtsi. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun dmc: dmc { 19*4882a593Smuzhiyun u-boot,dm-pre-reloc; 20*4882a593Smuzhiyun compatible = "rockchip,rk3399-dmc"; 21*4882a593Smuzhiyun devfreq-events = <&dfi>; 22*4882a593Smuzhiyun interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; 23*4882a593Smuzhiyun clocks = <&cru SCLK_DDRCLK>; 24*4882a593Smuzhiyun clock-names = "dmc_clk"; 25*4882a593Smuzhiyun reg = <0x0 0xffa80000 0x0 0x0800 26*4882a593Smuzhiyun 0x0 0xffa80800 0x0 0x1800 27*4882a593Smuzhiyun 0x0 0xffa82000 0x0 0x2000 28*4882a593Smuzhiyun 0x0 0xffa84000 0x0 0x1000 29*4882a593Smuzhiyun 0x0 0xffa88000 0x0 0x0800 30*4882a593Smuzhiyun 0x0 0xffa88800 0x0 0x1800 31*4882a593Smuzhiyun 0x0 0xffa8a000 0x0 0x2000 32*4882a593Smuzhiyun 0x0 0xffa8c000 0x0 0x1000>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun &dmc { 36*4882a593Smuzhiyun rockchip,sdram-params = < 37*4882a593Smuzhiyun 0x2 38*4882a593Smuzhiyun 0xa 39*4882a593Smuzhiyun 0x3 40*4882a593Smuzhiyun ... 41*4882a593Smuzhiyun >; 42*4882a593Smuzhiyun }; 43