1*4882a593Smuzhiyun* Microchip PIC32 Clock and Oscillator 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunMicrochip PIC32 clock tree consists of few oscillators, PLLs, 4*4882a593Smuzhiyunmultiplexers and few divider modules capable of supplying clocks 5*4882a593Smuzhiyunto various controllers within SoC and also to off-chip. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunPIC32 clock controller output is defined by indices as defined 8*4882a593Smuzhiyunin [0] 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun[0] include/dt-bindings/clock/microchip,clock.h 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunRequired Properties: 13*4882a593Smuzhiyun- compatible: should be "microchip,pic32mzda_clk" 14*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 15*4882a593Smuzhiyun region. 16*4882a593Smuzhiyun- #clock-cells: should be 1. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: Clock controller node: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun clock: clk@1f801200 { 21*4882a593Smuzhiyun compatible = "microchip,pic32mzda-clk"; 22*4882a593Smuzhiyun reg = <0x1f801200 0x1000>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: UART controller node that consumes the clock generated by the clock 26*4882a593Smuzhiyuncontroller: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun uart1: serial@1f822000 { 29*4882a593Smuzhiyun compatible = "microchip,pic32mzda-uart"; 30*4882a593Smuzhiyun reg = <0xbf822000 0x50>; 31*4882a593Smuzhiyun interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; 32*4882a593Smuzhiyun clocks = <&clock PB2CLK>; 33*4882a593Smuzhiyun }; 34