1*4882a593SmuzhiyunSandbox SPI/SPI Flash Implementation 2*4882a593Smuzhiyun==================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunU-Boot supports SPI and SPI flash emulation in sandbox. This must be enabled 5*4882a593Smuzhiyunusing the --spi_sf paramter when starting U-Boot. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunFor example: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun$ make O=sandbox sandbox_config 10*4882a593Smuzhiyun$ make O=sandbox 11*4882a593Smuzhiyun$ ./sandbox/u-boot --spi_sf 0:0:W25Q128:b/chromeos_peach/out/image.bin 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunThe four parameters to spi_sf are: 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun SPI bus number (typically 0) 16*4882a593Smuzhiyun SPI chip select number (typically 0) 17*4882a593Smuzhiyun SPI chip to emulate 18*4882a593Smuzhiyun File containing emulated data 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunSupported chips are W25Q16 (2MB), W25Q32 (4MB) and W25Q128 (16MB). Once 21*4882a593SmuzhiyunU-Boot it started you can use 'sf' commands as normal. For example: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun$ ./b/sandbox/u-boot --spi_sf 0:0:W25Q128:b/chromeos_peach/out/image.bin \ 24*4882a593Smuzhiyun -c "sf probe; sf test 0 100000; sf read 0 1000 1000; \ 25*4882a593Smuzhiyun sf erase 1000 1000; sf write 0 1000 1000" 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunU-Boot 2013.10-00237-gd4e0fdb (Nov 07 2013 - 20:08:15) 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunDRAM: 128 MiB 31*4882a593SmuzhiyunUsing default environment 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunIn: serial 34*4882a593SmuzhiyunOut: serial 35*4882a593SmuzhiyunErr: serial 36*4882a593SmuzhiyunSF: Detected W25Q128BV with page size 256 Bytes, erase size 4 KiB, total 16 MiB 37*4882a593SmuzhiyunSPI flash test: 38*4882a593Smuzhiyun0 erase: 1 ticks, 1024000 KiB/s 8192.000 Mbps 39*4882a593Smuzhiyun1 check: 2 ticks, 512000 KiB/s 4096.000 Mbps 40*4882a593Smuzhiyun2 write: 6 ticks, 170666 KiB/s 1365.328 Mbps 41*4882a593Smuzhiyun3 read: 0 ticks, 1048576000 KiB/s -201326.-592 Mbps 42*4882a593SmuzhiyunTest passed 43*4882a593Smuzhiyun0 erase: 1 ticks, 1024000 KiB/s 8192.000 Mbps 44*4882a593Smuzhiyun1 check: 2 ticks, 512000 KiB/s 4096.000 Mbps 45*4882a593Smuzhiyun2 write: 6 ticks, 170666 KiB/s 1365.328 Mbps 46*4882a593Smuzhiyun3 read: 0 ticks, 1048576000 KiB/s -201326.-592 Mbps 47*4882a593SmuzhiyunSF: 4096 bytes @ 0x1000 Read: OK 48*4882a593SmuzhiyunSF: 4096 bytes @ 0x1000 Erased: OK 49*4882a593SmuzhiyunSF: 4096 bytes @ 0x1000 Written: OK 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunSince the SPI bus is fully implemented as well as the SPI flash connected to 53*4882a593Smuzhiyunit, you can also use low-level SPI commands to access the flash. For example 54*4882a593Smuzhiyunthis reads the device ID from the emulated chip: 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun=> sspi 0 32 9f 57*4882a593SmuzhiyunFFEF4018 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun 60*4882a593SmuzhiyunSimon Glass 61*4882a593Smuzhiyunsjg@chromium.org 62*4882a593Smuzhiyun7/11/2013 63*4882a593SmuzhiyunNote that the sandbox SPI implementation was written by Mike Frysinger 64*4882a593Smuzhiyun<vapier@gentoo.org>. 65