1*4882a593SmuzhiyunSPI/QSPI Dual flash connection modes: 2*4882a593Smuzhiyun===================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThis describes how SPI/QSPI flash memories are connected to a given 5*4882a593Smuzhiyuncontroller in a single chip select line. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunCurrent spi_flash framework supports, single flash memory connected 8*4882a593Smuzhiyunto a given controller with single chip select line, but there are some 9*4882a593Smuzhiyunhw logics(ex: xilinx zynq qspi) that describes two/dual memories are 10*4882a593Smuzhiyunconnected with a single chip select line from a controller. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun"dual_flash" from include/spi.h describes these types of connection mode 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunPossible connections: 15*4882a593Smuzhiyun-------------------- 16*4882a593SmuzhiyunSF_SINGLE_FLASH: 17*4882a593Smuzhiyun - single spi flash memory connected with single chip select line. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun +------------+ CS +---------------+ 20*4882a593Smuzhiyun | |----------------------->| | 21*4882a593Smuzhiyun | Controller | I0[3:0] | Flash memory | 22*4882a593Smuzhiyun | SPI/QSPI |<======================>| (SPI/QSPI) | 23*4882a593Smuzhiyun | | CLK | | 24*4882a593Smuzhiyun | |----------------------->| | 25*4882a593Smuzhiyun +------------+ +---------------+ 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunSF_DUAL_STACKED_FLASH: 28*4882a593Smuzhiyun - dual spi/qspi flash memories are connected with a single chipselect 29*4882a593Smuzhiyun line and these two memories are operating stacked fasion with shared buses. 30*4882a593Smuzhiyun - xilinx zynq qspi controller has implemented this feature [1] 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun +------------+ CS +---------------+ 33*4882a593Smuzhiyun | |---------------------->| | 34*4882a593Smuzhiyun | | I0[3:0] | Upper Flash | 35*4882a593Smuzhiyun | | +=========>| memory | 36*4882a593Smuzhiyun | | | CLK | (SPI/QSPI) | 37*4882a593Smuzhiyun | | | +---->| | 38*4882a593Smuzhiyun | Controller | CS | | +---------------+ 39*4882a593Smuzhiyun | SPI/QSPI |------------|----|---->| | 40*4882a593Smuzhiyun | | I0[3:0] | | | Lower Flash | 41*4882a593Smuzhiyun | |<===========+====|====>| memory | 42*4882a593Smuzhiyun | | CLK | | (SPI/QSPI) | 43*4882a593Smuzhiyun | |-----------------+---->| | 44*4882a593Smuzhiyun +------------+ +---------------+ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun - two memory flash devices should has same hw part attributes (like size, 47*4882a593Smuzhiyun vendor..etc) 48*4882a593Smuzhiyun - Configurations: 49*4882a593Smuzhiyun on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG 50*4882a593Smuzhiyun Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory 51*4882a593Smuzhiyun Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory 52*4882a593Smuzhiyun - Operation: 53*4882a593Smuzhiyun accessing memories serially like one after another. 54*4882a593Smuzhiyun by default, if U_PAGE is unset lower memory should accessible, 55*4882a593Smuzhiyun once user wants to access upper memory need to set U_PAGE. 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunSPI_FLASH_CONN_DUALPARALLEL: 58*4882a593Smuzhiyun - dual spi/qspi flash memories are connected with a single chipselect 59*4882a593Smuzhiyun line and these two memories are operating parallel with separate buses. 60*4882a593Smuzhiyun - xilinx zynq qspi controller has implemented this feature [1] 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun +-------------+ CS +---------------+ 63*4882a593Smuzhiyun | |---------------------->| | 64*4882a593Smuzhiyun | | I0[3:0] | Upper Flash | 65*4882a593Smuzhiyun | |<=====================>| memory | 66*4882a593Smuzhiyun | | CLK | (SPI/QSPI) | 67*4882a593Smuzhiyun | |---------------------->| | 68*4882a593Smuzhiyun | Controller | CS +---------------+ 69*4882a593Smuzhiyun | SPI/QSPI |---------------------->| | 70*4882a593Smuzhiyun | | I0[3:0] | Lower Flash | 71*4882a593Smuzhiyun | |<=====================>| memory | 72*4882a593Smuzhiyun | | CLK | (SPI/QSPI) | 73*4882a593Smuzhiyun | |---------------------->| | 74*4882a593Smuzhiyun +-------------+ +---------------+ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun - two memory flash devices should has same hw part attributes (like size, 77*4882a593Smuzhiyun vendor..etc) 78*4882a593Smuzhiyun - Configurations: 79*4882a593Smuzhiyun Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register. 80*4882a593Smuzhiyun - Operation: 81*4882a593Smuzhiyun Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory 82*4882a593Smuzhiyun and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory. 83*4882a593Smuzhiyun 84*4882a593SmuzhiyunNote: Technically there is only one CS line from the controller, but 85*4882a593Smuzhiyunzynq qspi controller has an internal hw logic to enable additional CS 86*4882a593Smuzhiyunwhen controller is configured for dual memories. 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun-- 91*4882a593SmuzhiyunJagannadha Sutradharudu Teki <jaganna@xilinx.com> 92*4882a593Smuzhiyun05-01-2014. 93