1*4882a593SmuzhiyunDriver implementing the fuse API for Freescale's On-Chip OTP Controller (OCOTP) 2*4882a593Smuzhiyunon MXC 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThis IP can be found on the following SoCs: 5*4882a593Smuzhiyun - Vybrid VF610, 6*4882a593Smuzhiyun - i.MX6. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunNote that this IP is different from albeit similar to the IPs of the same name 9*4882a593Smuzhiyunthat can be found on the following SoCs: 10*4882a593Smuzhiyun - i.MX23, 11*4882a593Smuzhiyun - i.MX28, 12*4882a593Smuzhiyun - i.MX50. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunThe section numbers in this file refer to the i.MX6 Reference Manual. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunA fuse word contains 32 fuse bit slots, as explained in 46.2.1. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunA bank contains 8 fuse word slots, as explained in 46.2.1 and shown by the 19*4882a593Smuzhiyunmemory map in 46.4. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunSome fuse bit or word slots may not have the corresponding fuses actually 22*4882a593Smuzhiyunimplemented in the fusebox. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunSee the README files of the SoCs using this driver in order to know the 25*4882a593Smuzhiyunconventions used by U-Boot to store some specific data in the fuses, e.g. MAC 26*4882a593Smuzhiyunaddresses. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunFuse operations: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun Read 31*4882a593Smuzhiyun Read operations are implemented as read accesses to the shadow registers, 32*4882a593Smuzhiyun using "Bankx Wordy" from the memory map in 46.4. This is explained in 33*4882a593Smuzhiyun detail by the first two paragraphs in 46.2.1.2. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun Sense 36*4882a593Smuzhiyun Sense operations are implemented as the direct fusebox read explained by 37*4882a593Smuzhiyun the steps in 46.2.1.2. 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun Program 40*4882a593Smuzhiyun Program operations are implemented as explained by the steps in 46.2.1.3. 41*4882a593Smuzhiyun Following this operation, the shadow registers are not reloaded by the 42*4882a593Smuzhiyun hardware. 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun Override 45*4882a593Smuzhiyun Override operations are implemented as write accesses to the shadow 46*4882a593Smuzhiyun registers, as explained by the first paragraph in 46.2.1.3. 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunConfiguration: 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun CONFIG_MXC_OCOTP 51*4882a593Smuzhiyun Define this to enable the mxc_ocotp driver. 52