1*4882a593SmuzhiyunSpin table in cache 2*4882a593Smuzhiyun===================================== 3*4882a593SmuzhiyunAs specified by ePAPR v1.1, the spin table needs to be in cached memory. After 4*4882a593SmuzhiyunDDR is initialized and U-Boot relocates itself into DDR, the spin table is 5*4882a593Smuzhiyunaccessible for core 0. It is part of release.S, within 4KB range after 6*4882a593Smuzhiyun__secondary_start_page. For other cores to use the spin table, the booting 7*4882a593Smuzhiyunprocess is described below: 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunCore 0 sets up the reset page on the top 4K of memory (or 4GB if total memory 10*4882a593Smuzhiyunis more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless of 11*4882a593Smuzhiyunthe physical address of this page, with WIMGE=0b01010. Core 0 also enables boot 12*4882a593Smuzhiyunpage translation for secondary cores to use this page of memory. Then 4KB 13*4882a593Smuzhiyunmemory is copied from __secondary_start_page to the boot page, after flusing 14*4882a593Smuzhiyuncache because this page is mapped as normal DDR. Before copying the reset page, 15*4882a593Smuzhiyuncore 0 puts the physical address of the spin table (which is in release.S and 16*4882a593Smuzhiyunrelocated to the top of mapped memory) into a variable __spin_table_addr so 17*4882a593Smuzhiyunthat secondary cores can see it. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunWhen secondary cores boot up from 0xffff_f000 page, they only have one default 20*4882a593SmuzhiyunTLB. While booting, they set up another TLB in AS=1 space and jump into 21*4882a593Smuzhiyunthe new space. The new TLB covers the physical address of the spin table page, 22*4882a593Smuzhiyunwith WIMGE =0b00100. Now secondary cores can keep polling the spin table 23*4882a593Smuzhiyunwithout stress DDR bus because both the code and the spin table is in cache. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunFor the above to work, DDR has to set the 'M' bit of WIMGE, in order to keep 26*4882a593Smuzhiyuncache coherence. 27