1*4882a593Smuzhiyun 2*4882a593SmuzhiyunNotes for the MIPS architecture port of U-Boot 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunToolchains 5*4882a593Smuzhiyun---------- 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun http://www.denx.de/wiki/DULG/ELDK 8*4882a593Smuzhiyun ELDK < DULG < DENX 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun http://www.emdebian.org/crosstools.html 11*4882a593Smuzhiyun Embedded Debian -- Cross-development toolchains 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun http://buildroot.uclibc.org/ 14*4882a593Smuzhiyun Buildroot 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunKnown Issues 17*4882a593Smuzhiyun------------ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun Cache will be disabled before entering the loaded ELF image without 22*4882a593Smuzhiyun writing back and invalidating cache lines. This leads to cache 23*4882a593Smuzhiyun incoherency in most cases, unless the code gets loaded after U-Boot 24*4882a593Smuzhiyun re-initializes the cache. The more common uImage 'bootm' command does 25*4882a593Smuzhiyun not suffer this problem. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun [workaround] To avoid this cache incoherency, 28*4882a593Smuzhiyun 1) insert flush_cache(all) before calling dcache_disable(), or 29*4882a593Smuzhiyun 2) fix dcache_disable() to do both flushing and disabling cache. 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun * Note that Linux users need to kill dcache_disable() in do_bootelf_exec() 32*4882a593Smuzhiyun or override do_bootelf_exec() not to disable I-/D-caches, because most 33*4882a593Smuzhiyun Linux/MIPS ports don't re-enable caches after entering kernel_entry. 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunTODOs 36*4882a593Smuzhiyun----- 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun * Probe CPU types, I-/D-cache and TLB size etc. automatically 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun * Secondary cache support missing 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun * Initialize TLB entries redardless of their use 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun * R2000/R3000 class parts are not supported 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun * Limited testing across different MIPS variants 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun * Due to cache initialization issues, the DRAM on board must be 49*4882a593Smuzhiyun initialized in board specific assembler language before the cache init 50*4882a593Smuzhiyun code is run -- that is, initialize the DRAM in lowlevel_init(). 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun * centralize/share more CPU code of MIPS32, MIPS64 and XBurst 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun * support Qemu Malta 55