1*4882a593SmuzhiyunDriver implementing the fuse API for Freescale's IC Identification Module (IIM) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis IP can be found on the following SoCs: 4*4882a593Smuzhiyun - MPC512x, 5*4882a593Smuzhiyun - i.MX25, 6*4882a593Smuzhiyun - i.MX27, 7*4882a593Smuzhiyun - i.MX31, 8*4882a593Smuzhiyun - i.MX35, 9*4882a593Smuzhiyun - i.MX51, 10*4882a593Smuzhiyun - i.MX53. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunThe section numbers in this file refer to the i.MX25 Reference Manual. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunA fuse word contains 8 fuse bit slots, as explained in 30.4.2.2.1. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunA bank contains 256 fuse word slots, as shown by the memory map in 30.3.1. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunSome fuse bit or word slots may not have the corresponding fuses actually 19*4882a593Smuzhiyunimplemented in the fusebox. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunSee the README files of the SoCs using this driver in order to know the 22*4882a593Smuzhiyunconventions used by U-Boot to store some specific data in the fuses, e.g. MAC 23*4882a593Smuzhiyunaddresses. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunFuse operations: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun Read 28*4882a593Smuzhiyun Read operations are implemented as read accesses to the shadow registers, 29*4882a593Smuzhiyun using "Word y of Bank x" from the register summary in 30.3.2. This is 30*4882a593Smuzhiyun explained in detail in 30.4.5.1. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun Sense 33*4882a593Smuzhiyun Sense operations are implemented as explained in 30.4.5.2. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun Program 36*4882a593Smuzhiyun Program operations are implemented as explained in 30.4.5.3. Following 37*4882a593Smuzhiyun this operation, the shadow registers are reloaded by the hardware (not 38*4882a593Smuzhiyun immediately, but this does not make any difference for a user reading 39*4882a593Smuzhiyun these registers). 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun Override 42*4882a593Smuzhiyun Override operations are implemented as write accesses to the shadow 43*4882a593Smuzhiyun registers, as explained in 30.4.5.4. 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunConfiguration: 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun CONFIG_FSL_IIM 48*4882a593Smuzhiyun Define this to enable the fsl_iim driver. 49