1*4882a593SmuzhiyunU-Boot config options used in fec_mxc.c 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunCONFIG_FEC_MXC 4*4882a593Smuzhiyun Selects fec_mxc.c to be compiled into u-boot. Can read out the 5*4882a593Smuzhiyun ethaddr from the SoC eFuses (see below). 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunCONFIG_MII 8*4882a593Smuzhiyun Must be defined if CONFIG_FEC_MXC is defined. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunCONFIG_FEC_XCV_TYPE 11*4882a593Smuzhiyun Defaults to MII100 for 100 Base-tx. 12*4882a593Smuzhiyun RGMII selects 1000 Base-tx reduced pin count interface. 13*4882a593Smuzhiyun RMII selects 100 Base-tx reduced pin count interface. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunCONFIG_FEC_MXC_SWAP_PACKET 16*4882a593Smuzhiyun Forced on iff MX28. 17*4882a593Smuzhiyun Swaps the bytes order of all words(4 byte units) in the packet. 18*4882a593Smuzhiyun This should not be specified by a board file. It is cpu specific. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunCONFIG_PHYLIB 21*4882a593Smuzhiyun fec_mxc supports PHYLIB and should be used for new boards. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunCONFIG_FEC_MXC_NO_ANEG 24*4882a593Smuzhiyun Relevant only if PHYLIB not used. Skips auto-negotiation restart. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunCONFIG_FEC_MXC_PHYADDR 27*4882a593Smuzhiyun Optional, selects the exact phy address that should be connected 28*4882a593Smuzhiyun and function fecmxc_initialize will try to initialize it. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunCONFIG_FEC_FIXED_SPEED 31*4882a593Smuzhiyun Optional, selects a fixed speed on the MAC interface without asking some 32*4882a593Smuzhiyun phy. This is usefull if there is a direct MAC <-> MAC connection, for 33*4882a593Smuzhiyun example if the CPU is connected directly via the RGMII interface to a 34*4882a593Smuzhiyun ethernet-switch. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunReading the ethaddr from the SoC eFuses: 37*4882a593Smuzhiyunif CONFIG_FEC_MXC is defined and the U-Boot environment does not contain the 38*4882a593Smuzhiyunethaddr variable, then its value gets read from the corresponding eFuses in 39*4882a593Smuzhiyunthe SoC. See the README files of the specific SoC for details. 40