1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * (C) Copyright 2008-2009 3*4882a593Smuzhiyun * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de> 4*4882a593Smuzhiyun * Jens Scharsig <esw@bus-elektronik.de> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunU-Boot vcxk video controller driver 10*4882a593Smuzhiyun====================================== 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunBy defining CONFIG_VIDEO_VCXK this driver can be used with VC2K, VC4K and 13*4882a593SmuzhiyunVC8K devices on following boards: 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunboard | ARCH | Vendor 16*4882a593Smuzhiyun----------------------------------------------------------------------- 17*4882a593SmuzhiyunEB+CPU5282-T1 | MCF5282 | BuS Elektronik GmbH & Co. KG 18*4882a593SmuzhiyunEB+MCF-EVB123 | MCF5282 | BuS Elektronik GmbH & Co. KG 19*4882a593SmuzhiyunEB+CPUx9K2 | AT91RM9200 | BuS Elektronik GmbH & Co. KG 20*4882a593SmuzhiyunZLSA | AT91RM9200 | Ruf Telematik AG 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunDriver configuration 23*4882a593Smuzhiyun-------------------- 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunThe driver needs some defines to describe the target hardware: 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunCONFIG_SYS_VCXK_BASE 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun base address of VCxK hardware memory 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunCONFIG_SYS_VCXK_DEFAULT_LINEALIGN 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun defines the physical alignment of a pixel row 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunCONFIG_SYS_VCXK_DOUBLEBUFFERED 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun some boards that use vcxk prevent read from framebuffer memory. 38*4882a593Smuzhiyun define this option to enable double buffering (needs 16KiB RAM) 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunCONFIG_SYS_VCXK_<xxxx>_PIN 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun defines the number of the I/O line PIN in the port 43*4882a593Smuzhiyun valid values for <xxxx> are: 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun ACKNOWLEDGE 46*4882a593Smuzhiyun describes the acknowledge line from vcxk hardware 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun ENABLE 49*4882a593Smuzhiyun describes the enable line to vcxk hardware 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun INVERT 52*4882a593Smuzhiyun describes the invert line to vcxk hardware 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun RESET 55*4882a593Smuzhiyun describes the reset line to vcxk hardware 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun REQUEST 58*4882a593Smuzhiyun describes the request line to vcxk hardware 59*4882a593Smuzhiyun 60*4882a593SmuzhiyunCONFIG_SYS_VCXK_<xxxx>_PORT 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun defines the I/O port which is connected with the line 63*4882a593Smuzhiyun for valid values for <xxxx> see CONFIG_SYS_VCXK_<xxxx>_PIN 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunCONFIG_SYS_VCXK_<xxxx>_DDR 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun defines the register which configures the direction 68*4882a593Smuzhiyun for valid values for <xxxx> see CONFIG_SYS_VCXK_<xxxx>_PIN 69