1*4882a593SmuzhiyunDisabling I-cache: 2*4882a593Smuzhiyun- Set CONFIG_SYS_ICACHE_OFF 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunDisabling D-cache: 5*4882a593Smuzhiyun- Set CONFIG_SYS_DCACHE_OFF 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunEnabling I-cache: 8*4882a593Smuzhiyun- Make sure CONFIG_SYS_ICACHE_OFF is not set and call icache_enable(). 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunEnabling D-cache: 11*4882a593Smuzhiyun- Make sure CONFIG_SYS_DCACHE_OFF is not set and call dcache_enable(). 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunEnabling Caches at System Startup: 14*4882a593Smuzhiyun- Implement enable_caches() for your platform and enable the I-cache and 15*4882a593Smuzhiyun D-cache from this function. This function is called immediately 16*4882a593Smuzhiyun after relocation. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunGuidelines for Working with D-cache: 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunMemory to Peripheral DMA: 21*4882a593Smuzhiyun- Flush the buffer after the MPU writes the data and before the DMA is 22*4882a593Smuzhiyun initiated. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunPeripheral to Memory DMA: 25*4882a593Smuzhiyun- Invalidate the buffer before starting the DMA. In case there are any dirty 26*4882a593Smuzhiyun lines from the DMA buffer in the cache, subsequent cache-line replacements 27*4882a593Smuzhiyun may corrupt the buffer in memory while the DMA is still going on. Cache-line 28*4882a593Smuzhiyun replacement can happen if the CPU tries to bring some other memory locations 29*4882a593Smuzhiyun into the cache while the DMA is going on. 30*4882a593Smuzhiyun- Invalidate the buffer after the DMA is complete and before the MPU reads 31*4882a593Smuzhiyun it. This may be needed in addition to the invalidation before the DMA 32*4882a593Smuzhiyun mentioned above, because in some processors memory contents can spontaneously 33*4882a593Smuzhiyun come to the cache due to speculative memory access by the CPU. If this 34*4882a593Smuzhiyun happens with the DMA buffer while DMA is going on we have a coherency problem. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunBuffer Requirements: 37*4882a593Smuzhiyun- Any buffer that is invalidated(that is, typically the peripheral to 38*4882a593Smuzhiyun memory DMA buffer) should be aligned to cache-line boundary both at 39*4882a593Smuzhiyun at the beginning and at the end of the buffer. 40*4882a593Smuzhiyun- If the buffer is not cache-line aligned invalidation will be restricted 41*4882a593Smuzhiyun to the aligned part. That is, one cache-line at the respective boundary 42*4882a593Smuzhiyun may be left out while doing invalidation. 43*4882a593Smuzhiyun- A suitable buffer can be alloced on the stack using the 44*4882a593Smuzhiyun ALLOC_CACHE_ALIGN_BUFFER macro. 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunCleanup Before Linux: 47*4882a593Smuzhiyun- cleanup_before_linux() should flush the D-cache, invalidate I-cache, and 48*4882a593Smuzhiyun disable MMU and caches. 49*4882a593Smuzhiyun- The following sequence is advisable while disabling d-cache: 50*4882a593Smuzhiyun 1. dcache_disable() - flushes and disables d-cache 51*4882a593Smuzhiyun 2. invalidate_dcache_all() - invalid any entry that came to the cache 52*4882a593Smuzhiyun in the short period after the cache was flushed but before the 53*4882a593Smuzhiyun cache got disabled. 54