1*4882a593SmuzhiyunI2C Edge Conditions: 2*4882a593Smuzhiyun==================== 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun I2C devices may be left in a write state if a read was occuring 5*4882a593Smuzhiyun and the CPU was reset. This may result in EEPROM data corruption. 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun The edge condition is as follows: 8*4882a593Smuzhiyun 1) A read operation begins. 9*4882a593Smuzhiyun 2) I2C controller issues a start command. 10*4882a593Smuzhiyun 3) The I2C writes the device address. 11*4882a593Smuzhiyun 4) The CPU is reset at this point. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun Once the CPU reinitializes and the read is tried again: 14*4882a593Smuzhiyun 1) The I2C controller issues a start command. 15*4882a593Smuzhiyun 2) The I2C controller writes the device address. 16*4882a593Smuzhiyun 3) The I2C controller writes the offset. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun The EEPROM sees: 19*4882a593Smuzhiyun 1) START 20*4882a593Smuzhiyun 2) device address 21*4882a593Smuzhiyun 3) START "this start is ignored by most EEPROMs" 22*4882a593Smuzhiyun 4) device address "EEPROM interprets this as offset" 23*4882a593Smuzhiyun 5) Offset in device, "EEPROM interprets this as data to write" 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun The device will interpret this sequence as a WRITE command and 26*4882a593Smuzhiyun write rubbish into itself, i.e. the "offset" will be interpreted 27*4882a593Smuzhiyun as data to be written in location "device address". 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunNotes 30*4882a593Smuzhiyun----- 31*4882a593Smuzhiyun!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A AMCC 4xx BUG!!! 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunThis reset edge condition could possibly be present in every I2C 34*4882a593Smuzhiyuncontroller and device available. For boards where a I2C bus reset 35*4882a593Smuzhiyunfunction can be implemented a i2c_init_board() function should be 36*4882a593Smuzhiyunprovided and enabled by #define'ing CONFIG_SYS_I2C_INIT_BOARD in your 37*4882a593Smuzhiyunboard's config file. Note that this is NOT necessary when using the 38*4882a593Smuzhiyunbit-banging I2C driver (common/soft_i2c.c) as this already includes 39*4882a593Smuzhiyunthe I2C bus reset sequence. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunMany thanks to Bill Hunter for finding this serious BUG. 43*4882a593Smuzhiyunemail to: <williamhunter@attbi.com> 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunErik Theisen <etheisen@mindspring.com> 46*4882a593SmuzhiyunTue, 5 Mar 2002 23:02:19 -0500 (Wed 05:02 MET) 47