1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _NONDM_BOARD_HANDLE_H 8*4882a593Smuzhiyun #define _NONDM_BOARD_HANDLE_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun typedef void (*sysrest_request_t)(void enum sysreset_t type); 11*4882a593Smuzhiyun typedef int (*pinctrl_select_state_t)(enum uclass_id id, int devnum, 12*4882a593Smuzhiyun const char * statename); 13*4882a593Smuzhiyun typedef int (*clk_set_rate_t)(int clk_id, unsigned long rate); 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct nondm_ops { 16*4882a593Smuzhiyun clk_set_rate_t *clk_set_rate; 17*4882a593Smuzhiyun sysrest_request_t *sysreset_request; 18*4882a593Smuzhiyun pinctrl_select_state_t *pinctrl_select_state; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif 41