xref: /OK3568_Linux_fs/u-boot/cmd/fpga.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2000, 2001
3*4882a593Smuzhiyun  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun /*
9*4882a593Smuzhiyun  *  FPGA support
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <command.h>
13*4882a593Smuzhiyun #include <fpga.h>
14*4882a593Smuzhiyun #include <fs.h>
15*4882a593Smuzhiyun #include <malloc.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun /* Local functions */
18*4882a593Smuzhiyun static int fpga_get_op(char *opstr);
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /* Local defines */
21*4882a593Smuzhiyun enum {
22*4882a593Smuzhiyun 	FPGA_NONE = -1,
23*4882a593Smuzhiyun 	FPGA_INFO,
24*4882a593Smuzhiyun 	FPGA_LOAD,
25*4882a593Smuzhiyun 	FPGA_LOADB,
26*4882a593Smuzhiyun 	FPGA_DUMP,
27*4882a593Smuzhiyun 	FPGA_LOADMK,
28*4882a593Smuzhiyun 	FPGA_LOADP,
29*4882a593Smuzhiyun 	FPGA_LOADBP,
30*4882a593Smuzhiyun 	FPGA_LOADFS,
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */
34*4882a593Smuzhiyun /* command form:
35*4882a593Smuzhiyun  *   fpga <op> <device number> <data addr> <datasize>
36*4882a593Smuzhiyun  * where op is 'load', 'dump', or 'info'
37*4882a593Smuzhiyun  * If there is no device number field, the fpga environment variable is used.
38*4882a593Smuzhiyun  * If there is no data addr field, the fpgadata environment variable is used.
39*4882a593Smuzhiyun  * The info command requires no data address field.
40*4882a593Smuzhiyun  */
do_fpga(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])41*4882a593Smuzhiyun int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	int op, dev = FPGA_INVALID_DEVICE;
44*4882a593Smuzhiyun 	size_t data_size = 0;
45*4882a593Smuzhiyun 	void *fpga_data = NULL;
46*4882a593Smuzhiyun 	char *devstr = env_get("fpga");
47*4882a593Smuzhiyun 	char *datastr = env_get("fpgadata");
48*4882a593Smuzhiyun 	int rc = FPGA_FAIL;
49*4882a593Smuzhiyun 	int wrong_parms = 0;
50*4882a593Smuzhiyun #if defined(CONFIG_FIT)
51*4882a593Smuzhiyun 	const char *fit_uname = NULL;
52*4882a593Smuzhiyun 	ulong fit_addr;
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADFS)
55*4882a593Smuzhiyun 	fpga_fs_info fpga_fsinfo;
56*4882a593Smuzhiyun 	fpga_fsinfo.fstype = FS_TYPE_ANY;
57*4882a593Smuzhiyun #endif
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	if (devstr)
60*4882a593Smuzhiyun 		dev = (int) simple_strtoul(devstr, NULL, 16);
61*4882a593Smuzhiyun 	if (datastr)
62*4882a593Smuzhiyun 		fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	switch (argc) {
65*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADFS)
66*4882a593Smuzhiyun 	case 9:
67*4882a593Smuzhiyun 		fpga_fsinfo.blocksize = (unsigned int)
68*4882a593Smuzhiyun 					     simple_strtoul(argv[5], NULL, 16);
69*4882a593Smuzhiyun 		fpga_fsinfo.interface = argv[6];
70*4882a593Smuzhiyun 		fpga_fsinfo.dev_part = argv[7];
71*4882a593Smuzhiyun 		fpga_fsinfo.filename = argv[8];
72*4882a593Smuzhiyun #endif
73*4882a593Smuzhiyun 	case 5:		/* fpga <op> <dev> <data> <datasize> */
74*4882a593Smuzhiyun 		data_size = simple_strtoul(argv[4], NULL, 16);
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	case 4:		/* fpga <op> <dev> <data> */
77*4882a593Smuzhiyun #if defined(CONFIG_FIT)
78*4882a593Smuzhiyun 		if (fit_parse_subimage(argv[3], (ulong)fpga_data,
79*4882a593Smuzhiyun 				       &fit_addr, &fit_uname)) {
80*4882a593Smuzhiyun 			fpga_data = (void *)fit_addr;
81*4882a593Smuzhiyun 			debug("*  fpga: subimage '%s' from FIT image ",
82*4882a593Smuzhiyun 			      fit_uname);
83*4882a593Smuzhiyun 			debug("at 0x%08lx\n", fit_addr);
84*4882a593Smuzhiyun 		} else
85*4882a593Smuzhiyun #endif
86*4882a593Smuzhiyun 		{
87*4882a593Smuzhiyun 			fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
88*4882a593Smuzhiyun 			debug("*  fpga: cmdline image address = 0x%08lx\n",
89*4882a593Smuzhiyun 			      (ulong)fpga_data);
90*4882a593Smuzhiyun 		}
91*4882a593Smuzhiyun 		debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	case 3:		/* fpga <op> <dev | data addr> */
94*4882a593Smuzhiyun 		dev = (int)simple_strtoul(argv[2], NULL, 16);
95*4882a593Smuzhiyun 		debug("%s: device = %d\n", __func__, dev);
96*4882a593Smuzhiyun 		/* FIXME - this is a really weak test */
97*4882a593Smuzhiyun 		if ((argc == 3) && (dev > fpga_count())) {
98*4882a593Smuzhiyun 			/* must be buffer ptr */
99*4882a593Smuzhiyun 			debug("%s: Assuming buffer pointer in arg 3\n",
100*4882a593Smuzhiyun 			      __func__);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun #if defined(CONFIG_FIT)
103*4882a593Smuzhiyun 			if (fit_parse_subimage(argv[2], (ulong)fpga_data,
104*4882a593Smuzhiyun 					       &fit_addr, &fit_uname)) {
105*4882a593Smuzhiyun 				fpga_data = (void *)fit_addr;
106*4882a593Smuzhiyun 				debug("*  fpga: subimage '%s' from FIT image ",
107*4882a593Smuzhiyun 				      fit_uname);
108*4882a593Smuzhiyun 				debug("at 0x%08lx\n", fit_addr);
109*4882a593Smuzhiyun 			} else
110*4882a593Smuzhiyun #endif
111*4882a593Smuzhiyun 			{
112*4882a593Smuzhiyun 				fpga_data = (void *)(uintptr_t)dev;
113*4882a593Smuzhiyun 				debug("*  fpga: cmdline image addr = 0x%08lx\n",
114*4882a593Smuzhiyun 				      (ulong)fpga_data);
115*4882a593Smuzhiyun 			}
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 			debug("%s: fpga_data = 0x%lx\n",
118*4882a593Smuzhiyun 			      __func__, (ulong)fpga_data);
119*4882a593Smuzhiyun 			dev = FPGA_INVALID_DEVICE;	/* reset device num */
120*4882a593Smuzhiyun 		}
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	case 2:		/* fpga <op> */
123*4882a593Smuzhiyun 		op = (int)fpga_get_op(argv[1]);
124*4882a593Smuzhiyun 		break;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	default:
127*4882a593Smuzhiyun 		debug("%s: Too many or too few args (%d)\n", __func__, argc);
128*4882a593Smuzhiyun 		op = FPGA_NONE;	/* force usage display */
129*4882a593Smuzhiyun 		break;
130*4882a593Smuzhiyun 	}
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	if (dev == FPGA_INVALID_DEVICE) {
133*4882a593Smuzhiyun 		puts("FPGA device not specified\n");
134*4882a593Smuzhiyun 		op = FPGA_NONE;
135*4882a593Smuzhiyun 	}
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	switch (op) {
138*4882a593Smuzhiyun 	case FPGA_NONE:
139*4882a593Smuzhiyun 	case FPGA_INFO:
140*4882a593Smuzhiyun 		break;
141*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADFS)
142*4882a593Smuzhiyun 	case FPGA_LOADFS:
143*4882a593Smuzhiyun 		/* Blocksize can be zero */
144*4882a593Smuzhiyun 		if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
145*4882a593Smuzhiyun 		    !fpga_fsinfo.filename)
146*4882a593Smuzhiyun 			wrong_parms = 1;
147*4882a593Smuzhiyun #endif
148*4882a593Smuzhiyun 	case FPGA_LOAD:
149*4882a593Smuzhiyun 	case FPGA_LOADP:
150*4882a593Smuzhiyun 	case FPGA_LOADB:
151*4882a593Smuzhiyun 	case FPGA_LOADBP:
152*4882a593Smuzhiyun 	case FPGA_DUMP:
153*4882a593Smuzhiyun 		if (!fpga_data || !data_size)
154*4882a593Smuzhiyun 			wrong_parms = 1;
155*4882a593Smuzhiyun 		break;
156*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADMK)
157*4882a593Smuzhiyun 	case FPGA_LOADMK:
158*4882a593Smuzhiyun 		if (!fpga_data)
159*4882a593Smuzhiyun 			wrong_parms = 1;
160*4882a593Smuzhiyun 		break;
161*4882a593Smuzhiyun #endif
162*4882a593Smuzhiyun 	}
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	if (wrong_parms) {
165*4882a593Smuzhiyun 		puts("Wrong parameters for FPGA request\n");
166*4882a593Smuzhiyun 		op = FPGA_NONE;
167*4882a593Smuzhiyun 	}
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	switch (op) {
170*4882a593Smuzhiyun 	case FPGA_NONE:
171*4882a593Smuzhiyun 		return CMD_RET_USAGE;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	case FPGA_INFO:
174*4882a593Smuzhiyun 		rc = fpga_info(dev);
175*4882a593Smuzhiyun 		break;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	case FPGA_LOAD:
178*4882a593Smuzhiyun 		rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
179*4882a593Smuzhiyun 		break;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADP)
182*4882a593Smuzhiyun 	case FPGA_LOADP:
183*4882a593Smuzhiyun 		rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
184*4882a593Smuzhiyun 		break;
185*4882a593Smuzhiyun #endif
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	case FPGA_LOADB:
188*4882a593Smuzhiyun 		rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
189*4882a593Smuzhiyun 		break;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADBP)
192*4882a593Smuzhiyun 	case FPGA_LOADBP:
193*4882a593Smuzhiyun 		rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
194*4882a593Smuzhiyun 		break;
195*4882a593Smuzhiyun #endif
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADFS)
198*4882a593Smuzhiyun 	case FPGA_LOADFS:
199*4882a593Smuzhiyun 		rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
200*4882a593Smuzhiyun 		break;
201*4882a593Smuzhiyun #endif
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADMK)
204*4882a593Smuzhiyun 	case FPGA_LOADMK:
205*4882a593Smuzhiyun 		switch (genimg_get_format(fpga_data)) {
206*4882a593Smuzhiyun #if defined(CONFIG_IMAGE_FORMAT_LEGACY)
207*4882a593Smuzhiyun 		case IMAGE_FORMAT_LEGACY:
208*4882a593Smuzhiyun 			{
209*4882a593Smuzhiyun 				image_header_t *hdr =
210*4882a593Smuzhiyun 						(image_header_t *)fpga_data;
211*4882a593Smuzhiyun 				ulong data;
212*4882a593Smuzhiyun 				uint8_t comp;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 				comp = image_get_comp(hdr);
215*4882a593Smuzhiyun 				if (comp == IH_COMP_GZIP) {
216*4882a593Smuzhiyun #if defined(CONFIG_GZIP)
217*4882a593Smuzhiyun 					ulong image_buf = image_get_data(hdr);
218*4882a593Smuzhiyun 					data = image_get_load(hdr);
219*4882a593Smuzhiyun 					ulong image_size = ~0UL;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 					if (gunzip((void *)data, ~0UL,
222*4882a593Smuzhiyun 						   (void *)image_buf,
223*4882a593Smuzhiyun 						   &image_size) != 0) {
224*4882a593Smuzhiyun 						puts("GUNZIP: error\n");
225*4882a593Smuzhiyun 						return 1;
226*4882a593Smuzhiyun 					}
227*4882a593Smuzhiyun 					data_size = image_size;
228*4882a593Smuzhiyun #else
229*4882a593Smuzhiyun 					puts("Gunzip image is not supported\n");
230*4882a593Smuzhiyun 					return 1;
231*4882a593Smuzhiyun #endif
232*4882a593Smuzhiyun 				} else {
233*4882a593Smuzhiyun 					data = (ulong)image_get_data(hdr);
234*4882a593Smuzhiyun 					data_size = image_get_data_size(hdr);
235*4882a593Smuzhiyun 				}
236*4882a593Smuzhiyun 				rc = fpga_load(dev, (void *)data, data_size,
237*4882a593Smuzhiyun 					       BIT_FULL);
238*4882a593Smuzhiyun 			}
239*4882a593Smuzhiyun 			break;
240*4882a593Smuzhiyun #endif
241*4882a593Smuzhiyun #if defined(CONFIG_FIT)
242*4882a593Smuzhiyun 		case IMAGE_FORMAT_FIT:
243*4882a593Smuzhiyun 			{
244*4882a593Smuzhiyun 				const void *fit_hdr = (const void *)fpga_data;
245*4882a593Smuzhiyun 				int noffset;
246*4882a593Smuzhiyun 				const void *fit_data;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 				if (fit_uname == NULL) {
249*4882a593Smuzhiyun 					puts("No FIT subimage unit name\n");
250*4882a593Smuzhiyun 					return 1;
251*4882a593Smuzhiyun 				}
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 				if (!fit_check_format(fit_hdr)) {
254*4882a593Smuzhiyun 					puts("Bad FIT image format\n");
255*4882a593Smuzhiyun 					return 1;
256*4882a593Smuzhiyun 				}
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 				/* get fpga component image node offset */
259*4882a593Smuzhiyun 				noffset = fit_image_get_node(fit_hdr,
260*4882a593Smuzhiyun 							     fit_uname);
261*4882a593Smuzhiyun 				if (noffset < 0) {
262*4882a593Smuzhiyun 					printf("Can't find '%s' FIT subimage\n",
263*4882a593Smuzhiyun 					       fit_uname);
264*4882a593Smuzhiyun 					return 1;
265*4882a593Smuzhiyun 				}
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 				/* verify integrity */
268*4882a593Smuzhiyun 				if (!fit_image_verify(fit_hdr, noffset)) {
269*4882a593Smuzhiyun 					puts ("Bad Data Hash\n");
270*4882a593Smuzhiyun 					return 1;
271*4882a593Smuzhiyun 				}
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 				/* get fpga subimage data address and length */
274*4882a593Smuzhiyun 				if (fit_image_get_data(fit_hdr, noffset,
275*4882a593Smuzhiyun 						       &fit_data, &data_size)) {
276*4882a593Smuzhiyun 					puts("Fpga subimage data not found\n");
277*4882a593Smuzhiyun 					return 1;
278*4882a593Smuzhiyun 				}
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 				rc = fpga_load(dev, fit_data, data_size,
281*4882a593Smuzhiyun 					       BIT_FULL);
282*4882a593Smuzhiyun 			}
283*4882a593Smuzhiyun 			break;
284*4882a593Smuzhiyun #endif
285*4882a593Smuzhiyun 		default:
286*4882a593Smuzhiyun 			puts("** Unknown image type\n");
287*4882a593Smuzhiyun 			rc = FPGA_FAIL;
288*4882a593Smuzhiyun 			break;
289*4882a593Smuzhiyun 		}
290*4882a593Smuzhiyun 		break;
291*4882a593Smuzhiyun #endif
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	case FPGA_DUMP:
294*4882a593Smuzhiyun 		rc = fpga_dump(dev, fpga_data, data_size);
295*4882a593Smuzhiyun 		break;
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	default:
298*4882a593Smuzhiyun 		printf("Unknown operation\n");
299*4882a593Smuzhiyun 		return CMD_RET_USAGE;
300*4882a593Smuzhiyun 	}
301*4882a593Smuzhiyun 	return rc;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun /*
305*4882a593Smuzhiyun  * Map op to supported operations.  We don't use a table since we
306*4882a593Smuzhiyun  * would just have to relocate it from flash anyway.
307*4882a593Smuzhiyun  */
fpga_get_op(char * opstr)308*4882a593Smuzhiyun static int fpga_get_op(char *opstr)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun 	int op = FPGA_NONE;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	if (!strcmp("info", opstr))
313*4882a593Smuzhiyun 		op = FPGA_INFO;
314*4882a593Smuzhiyun 	else if (!strcmp("loadb", opstr))
315*4882a593Smuzhiyun 		op = FPGA_LOADB;
316*4882a593Smuzhiyun 	else if (!strcmp("load", opstr))
317*4882a593Smuzhiyun 		op = FPGA_LOAD;
318*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADP)
319*4882a593Smuzhiyun 	else if (!strcmp("loadp", opstr))
320*4882a593Smuzhiyun 		op = FPGA_LOADP;
321*4882a593Smuzhiyun #endif
322*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADBP)
323*4882a593Smuzhiyun 	else if (!strcmp("loadbp", opstr))
324*4882a593Smuzhiyun 		op = FPGA_LOADBP;
325*4882a593Smuzhiyun #endif
326*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADFS)
327*4882a593Smuzhiyun 	else if (!strcmp("loadfs", opstr))
328*4882a593Smuzhiyun 		op = FPGA_LOADFS;
329*4882a593Smuzhiyun #endif
330*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADMK)
331*4882a593Smuzhiyun 	else if (!strcmp("loadmk", opstr))
332*4882a593Smuzhiyun 		op = FPGA_LOADMK;
333*4882a593Smuzhiyun #endif
334*4882a593Smuzhiyun 	else if (!strcmp("dump", opstr))
335*4882a593Smuzhiyun 		op = FPGA_DUMP;
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	if (op == FPGA_NONE)
338*4882a593Smuzhiyun 		printf("Unknown fpga operation \"%s\"\n", opstr);
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	return op;
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADFS)
344*4882a593Smuzhiyun U_BOOT_CMD(fpga, 9, 1, do_fpga,
345*4882a593Smuzhiyun #else
346*4882a593Smuzhiyun U_BOOT_CMD(fpga, 6, 1, do_fpga,
347*4882a593Smuzhiyun #endif
348*4882a593Smuzhiyun 	   "loadable FPGA image support",
349*4882a593Smuzhiyun 	   "[operation type] [device number] [image address] [image size]\n"
350*4882a593Smuzhiyun 	   "fpga operations:\n"
351*4882a593Smuzhiyun 	   "  dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
352*4882a593Smuzhiyun 	   "  info\t[dev]\t\t\tlist known device information\n"
353*4882a593Smuzhiyun 	   "  load\t[dev] [address] [size]\tLoad device from memory buffer\n"
354*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADP)
355*4882a593Smuzhiyun 	   "  loadp\t[dev] [address] [size]\t"
356*4882a593Smuzhiyun 	   "Load device from memory buffer with partial bitstream\n"
357*4882a593Smuzhiyun #endif
358*4882a593Smuzhiyun 	   "  loadb\t[dev] [address] [size]\t"
359*4882a593Smuzhiyun 	   "Load device from bitstream buffer (Xilinx only)\n"
360*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADBP)
361*4882a593Smuzhiyun 	   "  loadbp\t[dev] [address] [size]\t"
362*4882a593Smuzhiyun 	   "Load device from bitstream buffer with partial bitstream"
363*4882a593Smuzhiyun 	   "(Xilinx only)\n"
364*4882a593Smuzhiyun #endif
365*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADFS)
366*4882a593Smuzhiyun 	   "Load device from filesystem (FAT by default) (Xilinx only)\n"
367*4882a593Smuzhiyun 	   "  loadfs [dev] [address] [image size] [blocksize] <interface>\n"
368*4882a593Smuzhiyun 	   "        [<dev[:part]>] <filename>\n"
369*4882a593Smuzhiyun #endif
370*4882a593Smuzhiyun #if defined(CONFIG_CMD_FPGA_LOADMK)
371*4882a593Smuzhiyun 	   "  loadmk [dev] [address]\tLoad device generated with mkimage"
372*4882a593Smuzhiyun #if defined(CONFIG_FIT)
373*4882a593Smuzhiyun 	   "\n"
374*4882a593Smuzhiyun 	   "\tFor loadmk operating on FIT format uImage address must include\n"
375*4882a593Smuzhiyun 	   "\tsubimage unit name in the form of addr:<subimg_uname>"
376*4882a593Smuzhiyun #endif
377*4882a593Smuzhiyun #endif
378*4882a593Smuzhiyun );
379