1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2019 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __CMD_DDR_TOOL_MEMTESTER_IO_MAP_H 7*4882a593Smuzhiyun #define __CMD_DDR_TOOL_MEMTESTER_IO_MAP_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define CPU_2_IO_ALIGN_LEN (16) /* 16 byte */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun int data_cpu_2_io(void *p, u32 len); 12*4882a593Smuzhiyun void data_cpu_2_io_init(void); 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #endif /* __CMD_DDR_TOOL_MEMTESTER_IO_MAP_H */ 15