1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
4 */
5
6 #include <common.h>
7 #include <asm/arch/sdram.h>
8 #include "io_map.h"
9
10 #define IO_TYPE_1_1_16 0 /* up1 1:1 mode 16bit */
11 #define IO_TYPE_1_1_32 1 /* up1 1:1 mode 32bit */
12 #define IO_TYPE_1_2 2 /* up1 1:2 mode */
13 #define IO_TYPE_2 3 /* up2 */
14
15 static u32 io_type;
16
17 /* len should be 16byte align */
data_cpu_2_io(void * p,u32 len)18 int data_cpu_2_io(void *p, u32 len)
19 {
20 uchar *val = p;
21 uchar buf[CPU_2_IO_ALIGN_LEN];
22 u32 i, j;
23
24 if ((len % sizeof(buf)) || !len)
25 return -1;
26
27 if (io_type == IO_TYPE_1_2) {
28 len /= sizeof(buf);
29 for (j = 0; j < len; j++) {
30 memset(buf, 0, sizeof(buf));
31 for (i = 0; i < sizeof(buf); i++)
32 buf[i] = val[(i % 4) * 4 + i / 4 + j * sizeof(buf)];
33 memcpy(&val[j * sizeof(buf)], buf, sizeof(buf));
34 }
35 } else if (io_type == IO_TYPE_1_1_32) {
36 len /= 8;
37 for (j = 0; j < len; j++) {
38 memset(buf, 0, sizeof(buf));
39 for (i = 0; i < 8; i++)
40 buf[i] = val[(i % 4) * 2 + i / 4 + j * 8];
41 memcpy(&val[j * 8], buf, 8);
42 }
43 }
44 /* IO_TYPE_2 and IO_TYPE_1_1_16 do nothing*/
45 return 0;
46 }
47
data_cpu_2_io_init(void)48 void data_cpu_2_io_init(void)
49 {
50 #if defined(CONFIG_ROCKCHIP_RK3036)
51 io_type = IO_TYPE_1_1_16;
52 #elif defined(CONFIG_ROCKCHIP_RK3228) || \
53 defined(CONFIG_ROCKCHIP_RV1108) || \
54 defined(CONFIG_ROCKCHIP_RK3368) || \
55 defined(CONFIG_ROCKCHIP_RK3366)
56 io_type = IO_TYPE_1_2;
57 #elif defined(CONFIG_ROCKCHIP_RK3128) || \
58 defined(CONFIG_ROCKCHIP_RK3288) || \
59 defined(CONFIG_ROCKCHIP_RK3288)
60 u32 bw;
61
62 bw = get_ddr_bw();
63 if (bw == 2)
64 io_type = IO_TYPE_1_1_32;
65 else
66 io_type = IO_TYPE_1_1_16;
67 #elif defined(CONFIG_ROCKCHIP_RK3328) || \
68 defined(CONFIG_ROCKCHIP_PX30) || \
69 defined(CONFIG_ROCKCHIP_RK1808)
70 io_type = IO_TYPE_2;
71 #else
72 io_type = IO_TYPE_2;
73 #endif
74 }
75
76