1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015
3*4882a593Smuzhiyun * Gerald Kerma <dreagle@doukki.net>
4*4882a593Smuzhiyun * Tony Dinh <mibodhi@gmail.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <miiphy.h>
11*4882a593Smuzhiyun #include <asm/arch/cpu.h>
12*4882a593Smuzhiyun #include <asm/arch/soc.h>
13*4882a593Smuzhiyun #include <asm/arch/mpp.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun #include "nsa310s.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun
board_early_init_f(void)19*4882a593Smuzhiyun int board_early_init_f(void)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun /*
22*4882a593Smuzhiyun * default gpio configuration
23*4882a593Smuzhiyun * There are maximum 64 gpios controlled through 2 sets of registers
24*4882a593Smuzhiyun * the below configuration configures mainly initial LED status
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH,
27*4882a593Smuzhiyun NSA310S_OE_LOW, NSA310S_OE_HIGH);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* (all LEDs & power off active high) */
30*4882a593Smuzhiyun /* Multi-Purpose Pins Functionality configuration */
31*4882a593Smuzhiyun static const u32 kwmpp_config[] = {
32*4882a593Smuzhiyun MPP0_NF_IO2,
33*4882a593Smuzhiyun MPP1_NF_IO3,
34*4882a593Smuzhiyun MPP2_NF_IO4,
35*4882a593Smuzhiyun MPP3_NF_IO5,
36*4882a593Smuzhiyun MPP4_NF_IO6,
37*4882a593Smuzhiyun MPP5_NF_IO7,
38*4882a593Smuzhiyun MPP6_SYSRST_OUTn,
39*4882a593Smuzhiyun MPP7_GPO,
40*4882a593Smuzhiyun MPP8_TW_SDA,
41*4882a593Smuzhiyun MPP9_TW_SCK,
42*4882a593Smuzhiyun MPP10_UART0_TXD,
43*4882a593Smuzhiyun MPP11_UART0_RXD,
44*4882a593Smuzhiyun MPP12_GPO,
45*4882a593Smuzhiyun MPP13_GPIO,
46*4882a593Smuzhiyun MPP14_GPIO,
47*4882a593Smuzhiyun MPP15_GPIO,
48*4882a593Smuzhiyun MPP16_GPIO,
49*4882a593Smuzhiyun MPP17_GPIO,
50*4882a593Smuzhiyun MPP18_NF_IO0,
51*4882a593Smuzhiyun MPP19_NF_IO1,
52*4882a593Smuzhiyun MPP20_GPIO,
53*4882a593Smuzhiyun MPP21_GPIO,
54*4882a593Smuzhiyun MPP22_GPIO,
55*4882a593Smuzhiyun MPP23_GPIO,
56*4882a593Smuzhiyun MPP24_GPIO,
57*4882a593Smuzhiyun MPP25_GPIO,
58*4882a593Smuzhiyun MPP26_GPIO,
59*4882a593Smuzhiyun MPP27_GPIO,
60*4882a593Smuzhiyun MPP28_GPIO,
61*4882a593Smuzhiyun MPP29_GPIO,
62*4882a593Smuzhiyun MPP30_GPIO,
63*4882a593Smuzhiyun MPP31_GPIO,
64*4882a593Smuzhiyun MPP32_GPIO,
65*4882a593Smuzhiyun MPP33_GPIO,
66*4882a593Smuzhiyun MPP34_GPIO,
67*4882a593Smuzhiyun MPP35_GPIO,
68*4882a593Smuzhiyun 0
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun kirkwood_mpp_conf(kwmpp_config, NULL);
71*4882a593Smuzhiyun return 0;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
board_init(void)74*4882a593Smuzhiyun int board_init(void)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun /* address of boot parameters */
77*4882a593Smuzhiyun gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun #ifdef CONFIG_RESET_PHY_R
reset_phy(void)83*4882a593Smuzhiyun void reset_phy(void)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun u16 reg;
86*4882a593Smuzhiyun u16 phyaddr;
87*4882a593Smuzhiyun char *name = "egiga0";
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun if (miiphy_set_current_dev(name))
90*4882a593Smuzhiyun return;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* read PHY dev address */
93*4882a593Smuzhiyun if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
94*4882a593Smuzhiyun printf("could not read PHY dev address\n");
95*4882a593Smuzhiyun return;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /* set RGMII delay */
99*4882a593Smuzhiyun miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
100*4882a593Smuzhiyun miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, ®);
101*4882a593Smuzhiyun reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
102*4882a593Smuzhiyun miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
103*4882a593Smuzhiyun miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* reset PHY */
106*4882a593Smuzhiyun if (miiphy_reset(name, phyaddr))
107*4882a593Smuzhiyun return;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /*
110*4882a593Smuzhiyun * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
111*4882a593Smuzhiyun * and has an MCU attached to the LED[2] via tristate interrupt
112*4882a593Smuzhiyun */
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* switch to LED register page */
115*4882a593Smuzhiyun miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
116*4882a593Smuzhiyun /* read out LED polarity register */
117*4882a593Smuzhiyun miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, ®);
118*4882a593Smuzhiyun /* clear 4, set 5 - LED2 low, tri-state */
119*4882a593Smuzhiyun reg &= ~(MV88E1318_LED2_4);
120*4882a593Smuzhiyun reg |= (MV88E1318_LED2_5);
121*4882a593Smuzhiyun /* write back LED polarity register */
122*4882a593Smuzhiyun miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
123*4882a593Smuzhiyun /* jump back to page 0, per the PHY chip documenation. */
124*4882a593Smuzhiyun miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun /* set PHY back to auto-negotiation mode */
127*4882a593Smuzhiyun miiphy_write(name, phyaddr, 0x4, 0x1e1);
128*4882a593Smuzhiyun miiphy_write(name, phyaddr, 0x9, 0x300);
129*4882a593Smuzhiyun /* downshift */
130*4882a593Smuzhiyun miiphy_write(name, phyaddr, 0x10, 0x3860);
131*4882a593Smuzhiyun miiphy_write(name, phyaddr, 0x0, 0x9140);
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun #endif /* CONFIG_RESET_PHY_R */
134