1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) Xilinx, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifdef __cplusplus 8*4882a593Smuzhiyun extern "C" { 9*4882a593Smuzhiyun #endif 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /*typedef unsigned int u32; */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /** do we need to make this name more unique ? **/ 14*4882a593Smuzhiyun /*extern u32 ps7_init_data[]; */ 15*4882a593Smuzhiyun extern unsigned long *ps7_ddr_init_data; 16*4882a593Smuzhiyun extern unsigned long *ps7_mio_init_data; 17*4882a593Smuzhiyun extern unsigned long *ps7_pll_init_data; 18*4882a593Smuzhiyun extern unsigned long *ps7_clock_init_data; 19*4882a593Smuzhiyun extern unsigned long *ps7_peripherals_init_data; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define OPCODE_EXIT 0U 22*4882a593Smuzhiyun #define OPCODE_CLEAR 1U 23*4882a593Smuzhiyun #define OPCODE_WRITE 2U 24*4882a593Smuzhiyun #define OPCODE_MASKWRITE 3U 25*4882a593Smuzhiyun #define OPCODE_MASKPOLL 4U 26*4882a593Smuzhiyun #define OPCODE_MASKDELAY 5U 27*4882a593Smuzhiyun #define NEW_PS7_ERR_CODE 1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Encode number of arguments in last nibble */ 30*4882a593Smuzhiyun #define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0) 31*4882a593Smuzhiyun #define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr 32*4882a593Smuzhiyun #define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val 33*4882a593Smuzhiyun #define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val 34*4882a593Smuzhiyun #define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask 35*4882a593Smuzhiyun #define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Returns codes of PS7_Init */ 38*4882a593Smuzhiyun #define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */ 39*4882a593Smuzhiyun #define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */ 40*4882a593Smuzhiyun #define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */ 41*4882a593Smuzhiyun #define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */ 42*4882a593Smuzhiyun #define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */ 43*4882a593Smuzhiyun #define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Silicon Versions */ 46*4882a593Smuzhiyun #define PCW_SILICON_VERSION_1 0 47*4882a593Smuzhiyun #define PCW_SILICON_VERSION_2 1 48*4882a593Smuzhiyun #define PCW_SILICON_VERSION_3 2 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ 51*4882a593Smuzhiyun #define PS7_POST_CONFIG 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Freq of all peripherals */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define APU_FREQ 650000000 56*4882a593Smuzhiyun #define DDR_FREQ 525000000 57*4882a593Smuzhiyun #define DCI_FREQ 10096154 58*4882a593Smuzhiyun #define QSPI_FREQ 200000000 59*4882a593Smuzhiyun #define SMC_FREQ 10000000 60*4882a593Smuzhiyun #define ENET0_FREQ 125000000 61*4882a593Smuzhiyun #define ENET1_FREQ 10000000 62*4882a593Smuzhiyun #define USB0_FREQ 60000000 63*4882a593Smuzhiyun #define USB1_FREQ 60000000 64*4882a593Smuzhiyun #define SDIO_FREQ 50000000 65*4882a593Smuzhiyun #define UART_FREQ 100000000 66*4882a593Smuzhiyun #define SPI_FREQ 10000000 67*4882a593Smuzhiyun #define I2C_FREQ 108333336 68*4882a593Smuzhiyun #define WDT_FREQ 108333336 69*4882a593Smuzhiyun #define TTC_FREQ 50000000 70*4882a593Smuzhiyun #define CAN_FREQ 10000000 71*4882a593Smuzhiyun #define PCAP_FREQ 200000000 72*4882a593Smuzhiyun #define TPIU_FREQ 200000000 73*4882a593Smuzhiyun #define FPGA0_FREQ 100000000 74*4882a593Smuzhiyun #define FPGA1_FREQ 142857132 75*4882a593Smuzhiyun #define FPGA2_FREQ 200000000 76*4882a593Smuzhiyun #define FPGA3_FREQ 50000000 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* For delay calculation using global registers*/ 80*4882a593Smuzhiyun #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 81*4882a593Smuzhiyun #define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 82*4882a593Smuzhiyun #define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 83*4882a593Smuzhiyun #define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun int ps7_config(unsigned long *); 86*4882a593Smuzhiyun int ps7_init(void); 87*4882a593Smuzhiyun int ps7_post_config(void); 88*4882a593Smuzhiyun int ps7_debug(void); 89*4882a593Smuzhiyun char *getPS7MessageInfo(unsigned key); 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun void perf_start_clock(void); 92*4882a593Smuzhiyun void perf_disable_clock(void); 93*4882a593Smuzhiyun void perf_reset_clock(void); 94*4882a593Smuzhiyun void perf_reset_and_start_timer(void); 95*4882a593Smuzhiyun int get_number_of_cycles_for_delay(unsigned int delay); 96*4882a593Smuzhiyun #ifdef __cplusplus 97*4882a593Smuzhiyun } 98*4882a593Smuzhiyun #endif 99