1*4882a593Smuzhiyun 2*4882a593Smuzhiyun /****************************************************************************** 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun *******************************************************************************/ 10*4882a593Smuzhiyun /****************************************************************************/ 11*4882a593Smuzhiyun /** 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * @file ps7_init.h 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * This file can be included in FSBL code 16*4882a593Smuzhiyun * to get prototype of ps7_init() function 17*4882a593Smuzhiyun * and error codes 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun *****************************************************************************/ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifdef __cplusplus 22*4882a593Smuzhiyun extern "C" { 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun //typedef unsigned int u32; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /** do we need to make this name more unique ? **/ 30*4882a593Smuzhiyun //extern u32 ps7_init_data[]; 31*4882a593Smuzhiyun extern unsigned long * ps7_ddr_init_data; 32*4882a593Smuzhiyun extern unsigned long * ps7_mio_init_data; 33*4882a593Smuzhiyun extern unsigned long * ps7_pll_init_data; 34*4882a593Smuzhiyun extern unsigned long * ps7_clock_init_data; 35*4882a593Smuzhiyun extern unsigned long * ps7_peripherals_init_data; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define OPCODE_EXIT 0U 40*4882a593Smuzhiyun #define OPCODE_CLEAR 1U 41*4882a593Smuzhiyun #define OPCODE_WRITE 2U 42*4882a593Smuzhiyun #define OPCODE_MASKWRITE 3U 43*4882a593Smuzhiyun #define OPCODE_MASKPOLL 4U 44*4882a593Smuzhiyun #define OPCODE_MASKDELAY 5U 45*4882a593Smuzhiyun #define NEW_PS7_ERR_CODE 1 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Encode number of arguments in last nibble */ 48*4882a593Smuzhiyun #define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) 49*4882a593Smuzhiyun #define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr 50*4882a593Smuzhiyun #define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val 51*4882a593Smuzhiyun #define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val 52*4882a593Smuzhiyun #define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask 53*4882a593Smuzhiyun #define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Returns codes of PS7_Init */ 56*4882a593Smuzhiyun #define PS7_INIT_SUCCESS (0) // 0 is success in good old C 57*4882a593Smuzhiyun #define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now 58*4882a593Smuzhiyun #define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out 59*4882a593Smuzhiyun #define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init 60*4882a593Smuzhiyun #define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit 61*4882a593Smuzhiyun #define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Silicon Versions */ 65*4882a593Smuzhiyun #define PCW_SILICON_VERSION_1 0 66*4882a593Smuzhiyun #define PCW_SILICON_VERSION_2 1 67*4882a593Smuzhiyun #define PCW_SILICON_VERSION_3 2 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ 70*4882a593Smuzhiyun #define PS7_POST_CONFIG 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Freq of all peripherals */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define APU_FREQ 666666687 75*4882a593Smuzhiyun #define DDR_FREQ 533333374 76*4882a593Smuzhiyun #define DCI_FREQ 10158731 77*4882a593Smuzhiyun #define QSPI_FREQ 200000000 78*4882a593Smuzhiyun #define SMC_FREQ 10000000 79*4882a593Smuzhiyun #define ENET0_FREQ 125000000 80*4882a593Smuzhiyun #define ENET1_FREQ 10000000 81*4882a593Smuzhiyun #define USB0_FREQ 60000000 82*4882a593Smuzhiyun #define USB1_FREQ 60000000 83*4882a593Smuzhiyun #define SDIO_FREQ 50000000 84*4882a593Smuzhiyun #define UART_FREQ 50000000 85*4882a593Smuzhiyun #define SPI_FREQ 10000000 86*4882a593Smuzhiyun #define I2C_FREQ 111111115 87*4882a593Smuzhiyun #define WDT_FREQ 111111115 88*4882a593Smuzhiyun #define TTC_FREQ 50000000 89*4882a593Smuzhiyun #define CAN_FREQ 10000000 90*4882a593Smuzhiyun #define PCAP_FREQ 200000000 91*4882a593Smuzhiyun #define TPIU_FREQ 200000000 92*4882a593Smuzhiyun #define FPGA0_FREQ 100000000 93*4882a593Smuzhiyun #define FPGA1_FREQ 142857132 94*4882a593Smuzhiyun #define FPGA2_FREQ 50000000 95*4882a593Smuzhiyun #define FPGA3_FREQ 50000000 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* For delay calculation using global registers*/ 99*4882a593Smuzhiyun #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 100*4882a593Smuzhiyun #define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 101*4882a593Smuzhiyun #define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 102*4882a593Smuzhiyun #define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun int ps7_config( unsigned long*); 105*4882a593Smuzhiyun int ps7_init(); 106*4882a593Smuzhiyun int ps7_post_config(); 107*4882a593Smuzhiyun int ps7_debug(); 108*4882a593Smuzhiyun char* getPS7MessageInfo(unsigned key); 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun void perf_start_clock(void); 111*4882a593Smuzhiyun void perf_disable_clock(void); 112*4882a593Smuzhiyun void perf_reset_clock(void); 113*4882a593Smuzhiyun void perf_reset_and_start_timer(); 114*4882a593Smuzhiyun int get_number_of_cycles_for_delay(unsigned int delay); 115*4882a593Smuzhiyun #ifdef __cplusplus 116*4882a593Smuzhiyun } 117*4882a593Smuzhiyun #endif 118