1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <fdtdec.h>
9*4882a593Smuzhiyun #include <fpga.h>
10*4882a593Smuzhiyun #include <mmc.h>
11*4882a593Smuzhiyun #include <zynqpl.h>
12*4882a593Smuzhiyun #include <asm/arch/hardware.h>
13*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
18*4882a593Smuzhiyun (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
19*4882a593Smuzhiyun static xilinx_desc fpga;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* It can be done differently */
22*4882a593Smuzhiyun static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
23*4882a593Smuzhiyun static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
24*4882a593Smuzhiyun static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
25*4882a593Smuzhiyun static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
26*4882a593Smuzhiyun static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
27*4882a593Smuzhiyun static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
28*4882a593Smuzhiyun static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
29*4882a593Smuzhiyun static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
30*4882a593Smuzhiyun static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
31*4882a593Smuzhiyun static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
32*4882a593Smuzhiyun #endif
33*4882a593Smuzhiyun
board_init(void)34*4882a593Smuzhiyun int board_init(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
37*4882a593Smuzhiyun (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
38*4882a593Smuzhiyun u32 idcode;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun idcode = zynq_slcr_get_idcode();
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun switch (idcode) {
43*4882a593Smuzhiyun case XILINX_ZYNQ_7007S:
44*4882a593Smuzhiyun fpga = fpga007s;
45*4882a593Smuzhiyun break;
46*4882a593Smuzhiyun case XILINX_ZYNQ_7010:
47*4882a593Smuzhiyun fpga = fpga010;
48*4882a593Smuzhiyun break;
49*4882a593Smuzhiyun case XILINX_ZYNQ_7012S:
50*4882a593Smuzhiyun fpga = fpga012s;
51*4882a593Smuzhiyun break;
52*4882a593Smuzhiyun case XILINX_ZYNQ_7014S:
53*4882a593Smuzhiyun fpga = fpga014s;
54*4882a593Smuzhiyun break;
55*4882a593Smuzhiyun case XILINX_ZYNQ_7015:
56*4882a593Smuzhiyun fpga = fpga015;
57*4882a593Smuzhiyun break;
58*4882a593Smuzhiyun case XILINX_ZYNQ_7020:
59*4882a593Smuzhiyun fpga = fpga020;
60*4882a593Smuzhiyun break;
61*4882a593Smuzhiyun case XILINX_ZYNQ_7030:
62*4882a593Smuzhiyun fpga = fpga030;
63*4882a593Smuzhiyun break;
64*4882a593Smuzhiyun case XILINX_ZYNQ_7035:
65*4882a593Smuzhiyun fpga = fpga035;
66*4882a593Smuzhiyun break;
67*4882a593Smuzhiyun case XILINX_ZYNQ_7045:
68*4882a593Smuzhiyun fpga = fpga045;
69*4882a593Smuzhiyun break;
70*4882a593Smuzhiyun case XILINX_ZYNQ_7100:
71*4882a593Smuzhiyun fpga = fpga100;
72*4882a593Smuzhiyun break;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun #endif
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
77*4882a593Smuzhiyun (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
78*4882a593Smuzhiyun fpga_init();
79*4882a593Smuzhiyun fpga_add(fpga_xilinx, &fpga);
80*4882a593Smuzhiyun #endif
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
board_late_init(void)85*4882a593Smuzhiyun int board_late_init(void)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
88*4882a593Smuzhiyun case ZYNQ_BM_QSPI:
89*4882a593Smuzhiyun env_set("modeboot", "qspiboot");
90*4882a593Smuzhiyun break;
91*4882a593Smuzhiyun case ZYNQ_BM_NAND:
92*4882a593Smuzhiyun env_set("modeboot", "nandboot");
93*4882a593Smuzhiyun break;
94*4882a593Smuzhiyun case ZYNQ_BM_NOR:
95*4882a593Smuzhiyun env_set("modeboot", "norboot");
96*4882a593Smuzhiyun break;
97*4882a593Smuzhiyun case ZYNQ_BM_SD:
98*4882a593Smuzhiyun env_set("modeboot", "sdboot");
99*4882a593Smuzhiyun break;
100*4882a593Smuzhiyun case ZYNQ_BM_JTAG:
101*4882a593Smuzhiyun env_set("modeboot", "jtagboot");
102*4882a593Smuzhiyun break;
103*4882a593Smuzhiyun default:
104*4882a593Smuzhiyun env_set("modeboot", "");
105*4882a593Smuzhiyun break;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun return 0;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun #ifdef CONFIG_DISPLAY_BOARDINFO
checkboard(void)112*4882a593Smuzhiyun int checkboard(void)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun puts("Board: Xilinx Zynq\n");
115*4882a593Smuzhiyun return 0;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun #endif
118*4882a593Smuzhiyun
zynq_board_read_rom_ethaddr(unsigned char * ethaddr)119*4882a593Smuzhiyun int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
122*4882a593Smuzhiyun defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
123*4882a593Smuzhiyun if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
124*4882a593Smuzhiyun CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
125*4882a593Smuzhiyun ethaddr, 6))
126*4882a593Smuzhiyun printf("I2C EEPROM MAC address read failed\n");
127*4882a593Smuzhiyun #endif
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun return 0;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
dram_init_banksize(void)133*4882a593Smuzhiyun int dram_init_banksize(void)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun fdtdec_setup_memory_banksize();
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun return 0;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
dram_init(void)140*4882a593Smuzhiyun int dram_init(void)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun if (fdtdec_setup_memory_size() != 0)
143*4882a593Smuzhiyun return -EINVAL;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun zynq_ddrc_init();
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun return 0;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun #else
dram_init(void)150*4882a593Smuzhiyun int dram_init(void)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun zynq_ddrc_init();
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun return 0;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun #endif
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