1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2007 Michal Simek 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Michal SIMEK <monstr@monstr.eu> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * CAUTION: This file is a faked configuration !!! 9*4882a593Smuzhiyun * There is no real target for the microblaze-generic 10*4882a593Smuzhiyun * configuration. You have to replace this file with 11*4882a593Smuzhiyun * the generated file from your Xilinx design flow. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define XILINX_BOARD_NAME microblaze-generic 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Microblaze is microblaze_0 */ 17*4882a593Smuzhiyun #define XILINX_FSL_NUMBER 3 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* GPIO is LEDs_4Bit*/ 20*4882a593Smuzhiyun #define XILINX_GPIO_BASEADDR 0x40000000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Flash Memory is FLASH_2Mx32 */ 23*4882a593Smuzhiyun #define XILINX_FLASH_START 0x2c000000 24*4882a593Smuzhiyun #define XILINX_FLASH_SIZE 0x00800000 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Watchdog IP is wxi_timebase_wdt_0 */ 27*4882a593Smuzhiyun #define XILINX_WATCHDOG_BASEADDR 0x50000000 28*4882a593Smuzhiyun #define XILINX_WATCHDOG_IRQ 1 29