1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2007 Michal Simek
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Michal SIMEK <monstr@monstr.eu>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun /* This is a board specific file. It's OK to include board specific
10*4882a593Smuzhiyun * header files */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <config.h>
14*4882a593Smuzhiyun #include <fdtdec.h>
15*4882a593Smuzhiyun #include <asm/processor.h>
16*4882a593Smuzhiyun #include <asm/microblaze_intc.h>
17*4882a593Smuzhiyun #include <asm/asm.h>
18*4882a593Smuzhiyun #include <asm/gpio.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #ifdef CONFIG_XILINX_GPIO
23*4882a593Smuzhiyun static int reset_pin = -1;
24*4882a593Smuzhiyun #endif
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun ulong ram_base;
27*4882a593Smuzhiyun
dram_init_banksize(void)28*4882a593Smuzhiyun int dram_init_banksize(void)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun gd->bd->bi_dram[0].start = ram_base;
31*4882a593Smuzhiyun gd->bd->bi_dram[0].size = get_effective_memsize();
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun return 0;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
dram_init(void)36*4882a593Smuzhiyun int dram_init(void)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun int node;
39*4882a593Smuzhiyun fdt_addr_t addr;
40*4882a593Smuzhiyun fdt_size_t size;
41*4882a593Smuzhiyun const void *blob = gd->fdt_blob;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
44*4882a593Smuzhiyun "memory", 7);
45*4882a593Smuzhiyun if (node == -FDT_ERR_NOTFOUND) {
46*4882a593Smuzhiyun debug("DRAM: Can't get memory node\n");
47*4882a593Smuzhiyun return 1;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun addr = fdtdec_get_addr_size(blob, node, "reg", &size);
50*4882a593Smuzhiyun if (addr == FDT_ADDR_T_NONE || size == 0) {
51*4882a593Smuzhiyun debug("DRAM: Can't get base address or size\n");
52*4882a593Smuzhiyun return 1;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun ram_base = addr;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun gd->ram_top = addr; /* In setup_dest_addr() is done +ram_size */
57*4882a593Smuzhiyun gd->ram_size = size;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
do_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])62*4882a593Smuzhiyun int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD
65*4882a593Smuzhiyun #ifdef CONFIG_XILINX_GPIO
66*4882a593Smuzhiyun if (reset_pin != -1)
67*4882a593Smuzhiyun gpio_direction_output(reset_pin, 1);
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #ifdef CONFIG_XILINX_TB_WATCHDOG
71*4882a593Smuzhiyun hw_watchdog_disable();
72*4882a593Smuzhiyun #endif
73*4882a593Smuzhiyun #endif
74*4882a593Smuzhiyun puts ("Reseting board\n");
75*4882a593Smuzhiyun __asm__ __volatile__ (" mts rmsr, r0;" \
76*4882a593Smuzhiyun "bra r0");
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun return 0;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
gpio_init(void)81*4882a593Smuzhiyun static int gpio_init(void)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun #ifdef CONFIG_XILINX_GPIO
84*4882a593Smuzhiyun reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1);
85*4882a593Smuzhiyun if (reset_pin != -1)
86*4882a593Smuzhiyun gpio_request(reset_pin, "reset_pin");
87*4882a593Smuzhiyun #endif
88*4882a593Smuzhiyun return 0;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
board_late_init(void)91*4882a593Smuzhiyun int board_late_init(void)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun gpio_init();
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return 0;
96*4882a593Smuzhiyun }
97