1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Extreme Engineering Solutions, Inc. 3*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2000 6*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun #include <asm/mmu.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 15*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 16*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 17*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 18*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 19*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 20*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 21*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 22*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 23*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 24*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 25*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 26*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 27*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 28*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 29*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 30*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* W**G* - NOR flashes */ 33*4882a593Smuzhiyun /* This will be changed to *I*G* after relocation to RAM. */ 34*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, 35*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 36*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_256M, 1), 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 39*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 40*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_1M, 1), 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* *I*G* - NAND flash */ 43*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, 44*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 45*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_1M, 1), 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #if CONFIG_PCI1 48*4882a593Smuzhiyun /* *I*G* - PCI MEM */ 49*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, 50*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_1G, 1), 52*4882a593Smuzhiyun #endif 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #if CONFIG_PCI2 55*4882a593Smuzhiyun /* *I*G* - PCI MEM */ 56*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, 57*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 58*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_256M, 1), 59*4882a593Smuzhiyun #endif 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) 62*4882a593Smuzhiyun /* *I*G* - PCI IO */ 63*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS, 64*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 65*4882a593Smuzhiyun 0, 5, BOOKE_PAGESZ_16M, 1), 66*4882a593Smuzhiyun #endif 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 70