1 /*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 #include <common.h>
8 #include <i2c.h>
9
10 #include <fsl_ddr_sdram.h>
11 #include <fsl_ddr_dimm_params.h>
12
get_spd(ddr2_spd_eeprom_t * spd,unsigned char i2c_address)13 void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
14 {
15 i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
16
17 /* We use soldered memory, but use an SPD EEPROM to describe it.
18 * The SPD has an unspecified dimm type, but the DDR2 initialization
19 * code requires a specific type to be specified. This sets the type
20 * as a standard unregistered SO-DIMM. */
21 if (spd->dimm_type == 0) {
22 spd->dimm_type = 0x4;
23 ((uchar *)spd)[63] += 0x4;
24 }
25 }
26
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)27 void fsl_ddr_board_options(memctl_options_t *popts,
28 dimm_params_t *pdimm,
29 unsigned int ctrl_num)
30 {
31 /*
32 * Factors to consider for clock adjust:
33 * - number of chips on bus
34 * - position of slot
35 * - DDR1 vs. DDR2?
36 * - ???
37 *
38 * This needs to be determined on a board-by-board basis.
39 * 0110 3/4 cycle late
40 * 0111 7/8 cycle late
41 */
42 popts->clk_adjust = 7;
43
44 /*
45 * Factors to consider for CPO:
46 * - frequency
47 * - ddr1 vs. ddr2
48 */
49 popts->cpo_override = 9;
50
51 /*
52 * Factors to consider for write data delay:
53 * - number of DIMMs
54 *
55 * 1 = 1/4 clock delay
56 * 2 = 1/2 clock delay
57 * 3 = 3/4 clock delay
58 * 4 = 1 clock delay
59 * 5 = 5/4 clock delay
60 * 6 = 3/2 clock delay
61 */
62 popts->write_data_delay = 3;
63
64 /*
65 * Factors to consider for half-strength driver enable:
66 * - number of DIMMs installed
67 */
68 popts->half_strength_driver_enable = 0;
69 }
70