1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2009 Extreme Engineering Solutions, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/processor.h>
9*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
10*4882a593Smuzhiyun #include <asm/mmu.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <fdt_support.h>
13*4882a593Smuzhiyun #include <pca953x.h>
14*4882a593Smuzhiyun #include "../common/fsl_8xxx_misc.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
19*4882a593Smuzhiyun extern void ft_board_pci_setup(void *blob, bd_t *bd);
20*4882a593Smuzhiyun #endif
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun * Print out which flash was booted from and if booting from the 2nd flash,
24*4882a593Smuzhiyun * swap flash chip selects to maintain consistent flash numbering/addresses.
25*4882a593Smuzhiyun */
flash_cs_fixup(void)26*4882a593Smuzhiyun static void flash_cs_fixup(void)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun int flash_sel;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun * Print boot dev and swap flash flash chip selects if booted from 2nd
32*4882a593Smuzhiyun * flash. Swapping chip selects presents user with a common memory
33*4882a593Smuzhiyun * map regardless of which flash was booted from.
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
36*4882a593Smuzhiyun CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
37*4882a593Smuzhiyun printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun if (flash_sel) {
40*4882a593Smuzhiyun set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
41*4882a593Smuzhiyun set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
44*4882a593Smuzhiyun set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
board_early_init_r(void)48*4882a593Smuzhiyun int board_early_init_r(void)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun /* Initialize PCA9557 devices */
51*4882a593Smuzhiyun pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
52*4882a593Smuzhiyun pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
53*4882a593Smuzhiyun pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
54*4882a593Smuzhiyun pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun flash_cs_fixup();
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return 0;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
dram_init(void)61*4882a593Smuzhiyun int dram_init(void)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun phys_size_t dram_size = fsl_ddr_sdram();
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
66*4882a593Smuzhiyun /* Initialize and enable DDR ECC */
67*4882a593Smuzhiyun ddr_enable_ecc(dram_size);
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun gd->ram_size = dram_size;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun return 0;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)76*4882a593Smuzhiyun int ft_board_setup(void *blob, bd_t *bd)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun #ifdef CONFIG_PCI
79*4882a593Smuzhiyun ft_board_pci_setup(blob, bd);
80*4882a593Smuzhiyun #endif
81*4882a593Smuzhiyun ft_cpu_setup(blob, bd);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return 0;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun #endif
86