1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2008 Extreme Engineering Solutions, Inc.
3*4882a593Smuzhiyun * Copyright 2007-2008 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <pci.h>
10*4882a593Smuzhiyun #include <asm/fsl_pci.h>
11*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <linux/compiler.h>
14*4882a593Smuzhiyun #include <linux/libfdt.h>
15*4882a593Smuzhiyun #include <fdt_support.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #ifdef CONFIG_PCI1
19*4882a593Smuzhiyun static struct pci_controller pci1_hose;
20*4882a593Smuzhiyun #endif
21*4882a593Smuzhiyun
pci_init_board(void)22*4882a593Smuzhiyun void pci_init_board(void)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun int first_free_busno = 0;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #ifdef CONFIG_PCI1
27*4882a593Smuzhiyun int pcie_ep;
28*4882a593Smuzhiyun struct fsl_pci_info pci_info;
29*4882a593Smuzhiyun volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
30*4882a593Smuzhiyun u32 devdisr = in_be32(&gur->devdisr);
31*4882a593Smuzhiyun uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
32*4882a593Smuzhiyun uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
33*4882a593Smuzhiyun uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
34*4882a593Smuzhiyun uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
35*4882a593Smuzhiyun uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
38*4882a593Smuzhiyun SET_STD_PCI_INFO(pci_info, 1);
39*4882a593Smuzhiyun set_next_law(pci_info.mem_phys,
40*4882a593Smuzhiyun law_size_bits(pci_info.mem_size), pci_info.law);
41*4882a593Smuzhiyun set_next_law(pci_info.io_phys,
42*4882a593Smuzhiyun law_size_bits(pci_info.io_size), pci_info.law);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
45*4882a593Smuzhiyun printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
46*4882a593Smuzhiyun pci_32 ? 32 : 64,
47*4882a593Smuzhiyun pcix ? "PCIX" : "PCI",
48*4882a593Smuzhiyun pci_spd_norm ? ">=" : "<=",
49*4882a593Smuzhiyun pcix ? freq * 2 : freq,
50*4882a593Smuzhiyun pcie_ep ? "agent" : "host",
51*4882a593Smuzhiyun pci_arb ? "arbiter" : "external-arbiter");
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun first_free_busno = fsl_pci_init_port(&pci_info,
54*4882a593Smuzhiyun &pci1_hose, first_free_busno);
55*4882a593Smuzhiyun } else {
56*4882a593Smuzhiyun printf("PCI1: disabled\n");
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun #elif defined CONFIG_ARCH_MPC8548
59*4882a593Smuzhiyun volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
60*4882a593Smuzhiyun /* PCI1 not present on MPC8572 */
61*4882a593Smuzhiyun setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
62*4882a593Smuzhiyun #endif
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun fsl_pcie_init_board(first_free_busno);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_pci_setup(void * blob,bd_t * bd)68*4882a593Smuzhiyun void ft_board_pci_setup(void *blob, bd_t *bd)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun FT_FSL_PCI_SETUP;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun #endif /* CONFIG_OF_BOARD_SETUP */
73