1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Extreme Engineering Solutions, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This driver support NAND devices which have address lines 5*4882a593Smuzhiyun * connected as ALE and CLE inputs. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <nand.h> 12*4882a593Smuzhiyun #include <asm/io.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Hardware specific access to control-lines 16*4882a593Smuzhiyun */ nand_addr_hwcontrol(struct mtd_info * mtd,int cmd,uint ctrl)17*4882a593Smuzhiyunstatic void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) 18*4882a593Smuzhiyun { 19*4882a593Smuzhiyun struct nand_chip *this = mtd_to_nand(mtd); 20*4882a593Smuzhiyun ulong IO_ADDR_W; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun if (ctrl & NAND_CTRL_CHANGE) { 23*4882a593Smuzhiyun IO_ADDR_W = (ulong)this->IO_ADDR_W; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE | 26*4882a593Smuzhiyun CONFIG_SYS_NAND_ACTL_ALE | 27*4882a593Smuzhiyun CONFIG_SYS_NAND_ACTL_NCE); 28*4882a593Smuzhiyun if (ctrl & NAND_CLE) 29*4882a593Smuzhiyun IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE; 30*4882a593Smuzhiyun if (ctrl & NAND_ALE) 31*4882a593Smuzhiyun IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE; 32*4882a593Smuzhiyun if (ctrl & NAND_NCE) 33*4882a593Smuzhiyun IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun this->IO_ADDR_W = (void *)IO_ADDR_W; 36*4882a593Smuzhiyun } 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun if (cmd != NAND_CMD_NONE) 39*4882a593Smuzhiyun writeb(cmd, this->IO_ADDR_W); 40*4882a593Smuzhiyun } 41*4882a593Smuzhiyun board_nand_init(struct nand_chip * nand)42*4882a593Smuzhiyunint board_nand_init(struct nand_chip *nand) 43*4882a593Smuzhiyun { 44*4882a593Smuzhiyun nand->ecc.mode = NAND_ECC_SOFT; 45*4882a593Smuzhiyun nand->cmd_ctrl = nand_addr_hwcontrol; 46*4882a593Smuzhiyun nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun return 0; 49*4882a593Smuzhiyun } 50