1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Author: Adrian Cox 3*4882a593Smuzhiyun * Based on corenet_ds tlb code 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <asm/mmu.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 12*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 13*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 14*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS, 15*4882a593Smuzhiyun MAS3_SW|MAS3_SR, 0, 16*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 17*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 18*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 19*4882a593Smuzhiyun MAS3_SW|MAS3_SR, 0, 20*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 21*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 22*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 23*4882a593Smuzhiyun MAS3_SW|MAS3_SR, 0, 24*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 25*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 26*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 27*4882a593Smuzhiyun MAS3_SW|MAS3_SR, 0, 28*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* TLB 1 */ 31*4882a593Smuzhiyun /* *I*** - Covers boot page */ 32*4882a593Smuzhiyun #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 35*4882a593Smuzhiyun * SRAM is at 0xfff00000, it covered the 0xfffff000. 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 38*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 39*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_1M, 1), 40*4882a593Smuzhiyun #else 41*4882a593Smuzhiyun SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 42*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 43*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 1), 44*4882a593Smuzhiyun #endif 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* *I*G* - CCSRBAR */ 47*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 48*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 49*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_16M, 1), 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Local Bus */ 52*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_LBC0_BASE, CONFIG_SYS_LBC0_BASE_PHYS, 53*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 54*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_64K, 1), 55*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_LBC1_BASE, CONFIG_SYS_LBC1_BASE_PHYS, 56*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_4K, 1), 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* *I*G* - PCI */ 60*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 61*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 62*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_1G, 1), 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* *I*G* - PCI */ 65*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 66*4882a593Smuzhiyun CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 67*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 68*4882a593Smuzhiyun 0, 5, BOOKE_PAGESZ_256M, 1), 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 71*4882a593Smuzhiyun CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 72*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 73*4882a593Smuzhiyun 0, 6, BOOKE_PAGESZ_256M, 1), 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* *I*G* - PCI I/O */ 76*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 77*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 78*4882a593Smuzhiyun 0, 7, BOOKE_PAGESZ_256K, 1), 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* Bman/Qman */ 81*4882a593Smuzhiyun #ifdef CONFIG_SYS_BMAN_MEM_PHYS 82*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 83*4882a593Smuzhiyun MAS3_SW|MAS3_SR, 0, 84*4882a593Smuzhiyun 0, 9, BOOKE_PAGESZ_1M, 1), 85*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, 86*4882a593Smuzhiyun CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, 87*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 88*4882a593Smuzhiyun 0, 10, BOOKE_PAGESZ_1M, 1), 89*4882a593Smuzhiyun #endif 90*4882a593Smuzhiyun #ifdef CONFIG_SYS_QMAN_MEM_PHYS 91*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 92*4882a593Smuzhiyun MAS3_SW|MAS3_SR, 0, 93*4882a593Smuzhiyun 0, 11, BOOKE_PAGESZ_1M, 1), 94*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, 95*4882a593Smuzhiyun CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, 96*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 97*4882a593Smuzhiyun 0, 12, BOOKE_PAGESZ_1M, 1), 98*4882a593Smuzhiyun #endif 99*4882a593Smuzhiyun #ifdef CONFIG_SYS_DCSRBAR_PHYS 100*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 101*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 102*4882a593Smuzhiyun 0, 13, BOOKE_PAGESZ_4M, 1), 103*4882a593Smuzhiyun #endif 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 107