1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Author Adrian Cox
3*4882a593Smuzhiyun * Based somewhat on board/freescale/corenet_ds/eth_hydra.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <netdev.h>
10*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
11*4882a593Smuzhiyun #include <fm_eth.h>
12*4882a593Smuzhiyun #include <fsl_mdio.h>
13*4882a593Smuzhiyun #include <malloc.h>
14*4882a593Smuzhiyun #include <fdt_support.h>
15*4882a593Smuzhiyun #include <fsl_dtsec.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #ifdef CONFIG_FMAN_ENET
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define FIRST_PORT_ADDR 3
20*4882a593Smuzhiyun #define SECOND_PORT_ADDR 7
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #ifdef CONFIG_ARCH_P5040
23*4882a593Smuzhiyun #define FIRST_PORT FM1_DTSEC5
24*4882a593Smuzhiyun #define SECOND_PORT FM2_DTSEC5
25*4882a593Smuzhiyun #else
26*4882a593Smuzhiyun #define FIRST_PORT FM1_DTSEC4
27*4882a593Smuzhiyun #define SECOND_PORT FM1_DTSEC5
28*4882a593Smuzhiyun #endif
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define IS_VALID_PORT(p) ((p) == FIRST_PORT || (p) == SECOND_PORT)
31*4882a593Smuzhiyun
cyrus_phy_tuning(int phy)32*4882a593Smuzhiyun static void cyrus_phy_tuning(int phy)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun /*
35*4882a593Smuzhiyun * Enable RGMII delay on Tx and Rx for CPU port
36*4882a593Smuzhiyun */
37*4882a593Smuzhiyun printf("Tuning PHY @ %d\n", phy);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* sets address 0x104 or reg 260 for writing */
40*4882a593Smuzhiyun miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8104);
41*4882a593Smuzhiyun /* Sets RXC/TXC to +0.96ns and TX_CTL/RX_CTL to -0.84ns */
42*4882a593Smuzhiyun miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0xf0f0);
43*4882a593Smuzhiyun /* sets address 0x105 or reg 261 for writing */
44*4882a593Smuzhiyun miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8105);
45*4882a593Smuzhiyun /* writes to address 0x105 , RXD[3..0] to -0. */
46*4882a593Smuzhiyun miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000);
47*4882a593Smuzhiyun /* sets address 0x106 or reg 261 for writing */
48*4882a593Smuzhiyun miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8106);
49*4882a593Smuzhiyun /* writes to address 0x106 , TXD[3..0] to -0.84ns */
50*4882a593Smuzhiyun miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000);
51*4882a593Smuzhiyun /* force re-negotiation */
52*4882a593Smuzhiyun miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0x0, 0x1340);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun #endif
55*4882a593Smuzhiyun
board_eth_init(bd_t * bis)56*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun #ifdef CONFIG_FMAN_ENET
59*4882a593Smuzhiyun struct fsl_pq_mdio_info dtsec_mdio_info;
60*4882a593Smuzhiyun unsigned int i;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun printf("Initializing Fman\n");
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Register the real 1G MDIO bus */
66*4882a593Smuzhiyun dtsec_mdio_info.regs =
67*4882a593Smuzhiyun (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
68*4882a593Smuzhiyun dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun fsl_pq_mdio_init(bis, &dtsec_mdio_info);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun fm_info_set_phy_address(FIRST_PORT, FIRST_PORT_ADDR);
74*4882a593Smuzhiyun fm_info_set_mdio(FIRST_PORT,
75*4882a593Smuzhiyun miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
76*4882a593Smuzhiyun fm_info_set_phy_address(SECOND_PORT, SECOND_PORT_ADDR);
77*4882a593Smuzhiyun fm_info_set_mdio(SECOND_PORT,
78*4882a593Smuzhiyun miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* Never disable DTSEC1 - it controls MDIO */
81*4882a593Smuzhiyun for (i = FM1_DTSEC2; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
82*4882a593Smuzhiyun if (!IS_VALID_PORT(i))
83*4882a593Smuzhiyun fm_disable_port(i);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #ifdef CONFIG_ARCH_P5040
87*4882a593Smuzhiyun for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
88*4882a593Smuzhiyun if (!IS_VALID_PORT(i))
89*4882a593Smuzhiyun fm_disable_port(i);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun #endif
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun cpu_eth_init(bis);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun cyrus_phy_tuning(FIRST_PORT_ADDR);
96*4882a593Smuzhiyun cyrus_phy_tuning(SECOND_PORT_ADDR);
97*4882a593Smuzhiyun #endif
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun return pci_eth_init(bis);
100*4882a593Smuzhiyun }
101