1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Marek Vasut <marex@denx.de>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <asm/addrspace.h>
10*4882a593Smuzhiyun #include <asm/types.h>
11*4882a593Smuzhiyun #include <mach/ath79.h>
12*4882a593Smuzhiyun #include <mach/ar71xx_regs.h>
13*4882a593Smuzhiyun #include <mach/ddr.h>
14*4882a593Smuzhiyun #include <debug_uart.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #ifdef CONFIG_USB
wdr4300_usb_start(void)19*4882a593Smuzhiyun static void wdr4300_usb_start(void)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE,
22*4882a593Smuzhiyun AR71XX_GPIO_SIZE, MAP_NOCACHE);
23*4882a593Smuzhiyun if (!gpio_regs)
24*4882a593Smuzhiyun return;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Power up the USB HUB. */
27*4882a593Smuzhiyun clrbits_be32(gpio_regs + AR71XX_GPIO_REG_OE, BIT(21) | BIT(22));
28*4882a593Smuzhiyun writel(BIT(21) | BIT(22), gpio_regs + AR71XX_GPIO_REG_SET);
29*4882a593Smuzhiyun mdelay(1);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun ath79_usb_reset();
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun #else
wdr4300_usb_start(void)34*4882a593Smuzhiyun static inline void wdr4300_usb_start(void) {}
35*4882a593Smuzhiyun #endif
36*4882a593Smuzhiyun
wdr4300_pinmux_config(void)37*4882a593Smuzhiyun void wdr4300_pinmux_config(void)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun void __iomem *regs;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
42*4882a593Smuzhiyun MAP_NOCACHE);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* Assure JTAG is not disconnected. */
45*4882a593Smuzhiyun writel(0x40, regs + AR934X_GPIO_REG_FUNC);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* Configure default GPIO input/output regs. */
48*4882a593Smuzhiyun writel(0x3031b, regs + AR71XX_GPIO_REG_OE);
49*4882a593Smuzhiyun writel(0x0f804, regs + AR71XX_GPIO_REG_OUT);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Configure pin multiplexing. */
52*4882a593Smuzhiyun writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC0);
53*4882a593Smuzhiyun writel(0x0b0a0980, regs + AR934X_GPIO_REG_OUT_FUNC1);
54*4882a593Smuzhiyun writel(0x00180000, regs + AR934X_GPIO_REG_OUT_FUNC2);
55*4882a593Smuzhiyun writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC3);
56*4882a593Smuzhiyun writel(0x0000004d, regs + AR934X_GPIO_REG_OUT_FUNC4);
57*4882a593Smuzhiyun writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC5);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)61*4882a593Smuzhiyun void board_debug_uart_init(void)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun wdr4300_pinmux_config();
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun #endif
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)68*4882a593Smuzhiyun int board_early_init_f(void)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun #ifndef CONFIG_DEBUG_UART_BOARD_INIT
71*4882a593Smuzhiyun wdr4300_pinmux_config();
72*4882a593Smuzhiyun #endif
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #ifndef CONFIG_SKIP_LOWLEVEL_INIT
75*4882a593Smuzhiyun ar934x_pll_init(560, 480, 240);
76*4882a593Smuzhiyun ar934x_ddr_init(560, 480, 240);
77*4882a593Smuzhiyun #endif
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun wdr4300_usb_start();
80*4882a593Smuzhiyun ath79_eth_reset();
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun #endif
85