1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Toradex Colibri PXA270 Support
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5*4882a593Smuzhiyun * Copyright (C) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <dm.h>
12*4882a593Smuzhiyun #include <asm/arch/hardware.h>
13*4882a593Smuzhiyun #include <asm/arch/pxa.h>
14*4882a593Smuzhiyun #include <asm/arch/regs-mmc.h>
15*4882a593Smuzhiyun #include <asm/arch/regs-uart.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun #include <dm/platdata.h>
18*4882a593Smuzhiyun #include <dm/platform_data/serial_pxa.h>
19*4882a593Smuzhiyun #include <netdev.h>
20*4882a593Smuzhiyun #include <serial.h>
21*4882a593Smuzhiyun #include <usb.h>
22*4882a593Smuzhiyun #include <asm/mach-types.h>
23*4882a593Smuzhiyun #include "../common/tdx-common.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
26*4882a593Smuzhiyun
board_init(void)27*4882a593Smuzhiyun int board_init(void)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun /* We have RAM, disable cache */
30*4882a593Smuzhiyun dcache_disable();
31*4882a593Smuzhiyun icache_disable();
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* arch number of Toradex Colibri PXA270 */
34*4882a593Smuzhiyun gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* adress of boot parameters */
37*4882a593Smuzhiyun gd->bd->bi_boot_params = 0xa0000100;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return 0;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
checkboard(void)42*4882a593Smuzhiyun int checkboard(void)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun puts("Model: Toradex Colibri PXA270\n");
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun return 0;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)50*4882a593Smuzhiyun int ft_board_setup(void *blob, bd_t *bd)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun return ft_common_board_setup(blob, bd);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun #endif
55*4882a593Smuzhiyun
dram_init(void)56*4882a593Smuzhiyun int dram_init(void)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun pxa2xx_dram_init();
59*4882a593Smuzhiyun gd->ram_size = PHYS_SDRAM_1_SIZE;
60*4882a593Smuzhiyun return 0;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #ifdef CONFIG_CMD_USB
board_usb_init(int index,enum usb_init_type init)64*4882a593Smuzhiyun int board_usb_init(int index, enum usb_init_type init)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
67*4882a593Smuzhiyun ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
68*4882a593Smuzhiyun UHCHR);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun while (UHCHR & UHCHR_FSBIR)
73*4882a593Smuzhiyun ;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
76*4882a593Smuzhiyun writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* Clear any OTG Pin Hold */
79*4882a593Smuzhiyun if (readl(PSSR) & PSSR_OTGPH)
80*4882a593Smuzhiyun writel(readl(PSSR) | PSSR_OTGPH, PSSR);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
83*4882a593Smuzhiyun writel(readl(UHCRHDA) | 0x100, UHCRHDA);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* Set port power control mask bits, only 3 ports. */
86*4882a593Smuzhiyun writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* enable port 2 */
89*4882a593Smuzhiyun writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
90*4882a593Smuzhiyun UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
board_usb_cleanup(int index,enum usb_init_type init)95*4882a593Smuzhiyun int board_usb_cleanup(int index, enum usb_init_type init)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
usb_board_stop(void)100*4882a593Smuzhiyun void usb_board_stop(void)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
103*4882a593Smuzhiyun udelay(11);
104*4882a593Smuzhiyun writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun writel(readl(UHCCOMS) | 1, UHCCOMS);
107*4882a593Smuzhiyun udelay(10);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun return;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun #endif
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_DM9000
board_eth_init(bd_t * bis)116*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun return dm9000_initialize(bis);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun #endif
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun #ifdef CONFIG_CMD_MMC
board_mmc_init(bd_t * bis)123*4882a593Smuzhiyun int board_mmc_init(bd_t *bis)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun pxa_mmc_register(0);
126*4882a593Smuzhiyun return 0;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun #endif
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun static const struct pxa_serial_platdata serial_platdata = {
131*4882a593Smuzhiyun .base = (struct pxa_uart_regs *)FFUART_BASE,
132*4882a593Smuzhiyun .port = FFUART_INDEX,
133*4882a593Smuzhiyun .baudrate = CONFIG_BAUDRATE,
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun U_BOOT_DEVICE(pxa_serials) = {
137*4882a593Smuzhiyun .name = "serial_pxa",
138*4882a593Smuzhiyun .platdata = &serial_platdata,
139*4882a593Smuzhiyun };
140