1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2015 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 2015 Toradex AG 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Refer doc/README.imximage for more details about how-to configure 8*4882a593Smuzhiyun * and create imximage boot image 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * The syntax is taken as close as possible with the kwbimage 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#define __ASSEMBLY__ 14*4882a593Smuzhiyun#include <config.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/* image version */ 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunIMAGE_VERSION 2 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun/* 21*4882a593Smuzhiyun * Boot Device : sd 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunBOOT_FROM sd 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun/* 27*4882a593Smuzhiyun * Secure boot support 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun#ifdef CONFIG_SECURE_BOOT 30*4882a593SmuzhiyunCSF CONFIG_CSF_SIZE 31*4882a593Smuzhiyun#endif 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun/* 34*4882a593Smuzhiyun * Device Configuration Data (DCD) 35*4882a593Smuzhiyun * 36*4882a593Smuzhiyun * Each entry must have the format: 37*4882a593Smuzhiyun * Addr-type Address Value 38*4882a593Smuzhiyun * 39*4882a593Smuzhiyun * where: 40*4882a593Smuzhiyun * Addr-type register length (1,2 or 4 bytes) 41*4882a593Smuzhiyun * Address absolute address of the register 42*4882a593Smuzhiyun * value value to be stored in the register 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun/* IOMUXC_GPR_GPR1 */ 46*4882a593SmuzhiyunDATA 4 0x30340004 0x4F400005 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun/* DDR3L */ 49*4882a593Smuzhiyun/* assuming MEMC_FREQ_RATIO = 2 */ 50*4882a593Smuzhiyun/* SRC_DDRC_RCR */ 51*4882a593SmuzhiyunDATA 4 0x30391000 0x00000002 52*4882a593Smuzhiyun/* DDRC_MSTR */ 53*4882a593SmuzhiyunDATA 4 0x307a0000 0x01040001 54*4882a593Smuzhiyun/* DDRC_DFIUPD0 */ 55*4882a593SmuzhiyunDATA 4 0x307a01a0 0x80400003 56*4882a593Smuzhiyun/* DDRC_DFIUPD1 */ 57*4882a593SmuzhiyunDATA 4 0x307a01a4 0x00100020 58*4882a593Smuzhiyun/* DDRC_DFIUPD2 */ 59*4882a593SmuzhiyunDATA 4 0x307a01a8 0x80100004 60*4882a593Smuzhiyun/* DDRC_RFSHTMG */ 61*4882a593SmuzhiyunDATA 4 0x307a0064 0x00400045 62*4882a593Smuzhiyun/* DDRC_MP_PCTRL_0 */ 63*4882a593SmuzhiyunDATA 4 0x307a0490 0x00000001 64*4882a593Smuzhiyun/* DDRC_INIT0 */ 65*4882a593SmuzhiyunDATA 4 0x307a00d0 0x00020083 66*4882a593Smuzhiyun/* DDRC_INIT1 */ 67*4882a593SmuzhiyunDATA 4 0x307a00d4 0x00690000 68*4882a593Smuzhiyun/* DDRC_INIT3 MR0/MR1 */ 69*4882a593SmuzhiyunDATA 4 0x307a00dc 0x09300004 70*4882a593Smuzhiyun/* DDRC_INIT4 MR2/MR3 */ 71*4882a593SmuzhiyunDATA 4 0x307a00e0 0x04480000 72*4882a593Smuzhiyun/* DDRC_INIT5 */ 73*4882a593SmuzhiyunDATA 4 0x307a00e4 0x00100004 74*4882a593Smuzhiyun/* DDRC_RANKCTL */ 75*4882a593SmuzhiyunDATA 4 0x307a00f4 0x0000033f 76*4882a593Smuzhiyun/* DDRC_DRAMTMG0 */ 77*4882a593SmuzhiyunDATA 4 0x307a0100 0x090b090a 78*4882a593Smuzhiyun/* DDRC_DRAMTMG1 */ 79*4882a593SmuzhiyunDATA 4 0x307a0104 0x000d020d 80*4882a593Smuzhiyun/* DDRC_DRAMTMG2 */ 81*4882a593SmuzhiyunDATA 4 0x307a0108 0x03040307 82*4882a593Smuzhiyun/* DDRC_DRAMTMG3 */ 83*4882a593SmuzhiyunDATA 4 0x307a010c 0x00002006 84*4882a593Smuzhiyun/* DDRC_DRAMTMG4 */ 85*4882a593SmuzhiyunDATA 4 0x307a0110 0x04020205 86*4882a593Smuzhiyun/* DDRC_DRAMTMG5 */ 87*4882a593SmuzhiyunDATA 4 0x307a0114 0x03030202 88*4882a593Smuzhiyun/* DDRC_DRAMTMG8 */ 89*4882a593SmuzhiyunDATA 4 0x307a0120 0x00000803 90*4882a593Smuzhiyun/* DDRC_ZQCTL0 */ 91*4882a593SmuzhiyunDATA 4 0x307a0180 0x00800020 92*4882a593Smuzhiyun/* DDRC_ZQCTL1 */ 93*4882a593SmuzhiyunDATA 4 0x307a0184 0x02001000 94*4882a593Smuzhiyun/* DDRC_DFITMG0 */ 95*4882a593SmuzhiyunDATA 4 0x307a0190 0x02098204 96*4882a593Smuzhiyun/* DDRC_DFITMG1 */ 97*4882a593SmuzhiyunDATA 4 0x307a0194 0x00030303 98*4882a593Smuzhiyun/* DDRC_ADDRMAP0 */ 99*4882a593SmuzhiyunDATA 4 0x307a0200 0x0000001f 100*4882a593Smuzhiyun/* DDRC_ADDRMAP1 */ 101*4882a593SmuzhiyunDATA 4 0x307a0204 0x00080808 102*4882a593Smuzhiyun/* DDRC_ADDRMAP5 */ 103*4882a593SmuzhiyunDATA 4 0x307a0214 0x07070707 104*4882a593Smuzhiyun/* DDRC_ADDRMAP6 */ 105*4882a593SmuzhiyunDATA 4 0x307a0218 0x07070707 106*4882a593Smuzhiyun/* DDRC_ODTCFG */ 107*4882a593SmuzhiyunDATA 4 0x307a0240 0x06000601 108*4882a593Smuzhiyun/* DDRC_ODTMAP */ 109*4882a593SmuzhiyunDATA 4 0x307a0244 0x00000011 110*4882a593Smuzhiyun/* SRC_DDRC_RCR */ 111*4882a593SmuzhiyunDATA 4 0x30391000 0x00000000 112*4882a593Smuzhiyun/* DDR_PHY_PHY_CON0 */ 113*4882a593SmuzhiyunDATA 4 0x30790000 0x17420f40 114*4882a593Smuzhiyun/* DDR_PHY_PHY_CON1 */ 115*4882a593SmuzhiyunDATA 4 0x30790004 0x10210100 116*4882a593Smuzhiyun/* DDR_PHY_PHY_CON4 */ 117*4882a593SmuzhiyunDATA 4 0x30790010 0x00060807 118*4882a593Smuzhiyun/* DDR_PHY_MDLL_CON0 */ 119*4882a593SmuzhiyunDATA 4 0x307900b0 0x1010007e 120*4882a593Smuzhiyun/* DDR_PHY_DRVDS_CON0 */ 121*4882a593SmuzhiyunDATA 4 0x3079009c 0x00000d6e 122*4882a593Smuzhiyun/* DDR_PHY_OFFSET_RD_CON0 */ 123*4882a593SmuzhiyunDATA 4 0x30790020 0x08080808 124*4882a593Smuzhiyun/* DDR_PHY_OFFSET_WR_CON0 */ 125*4882a593SmuzhiyunDATA 4 0x30790030 0x08080808 126*4882a593Smuzhiyun/* DDR_PHY_CMD_SDLL_CON0 */ 127*4882a593SmuzhiyunDATA 4 0x30790050 0x01000010 128*4882a593SmuzhiyunDATA 4 0x30790050 0x00000010 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun/* DDR_PHY_ZQ_CON0 */ 131*4882a593SmuzhiyunDATA 4 0x307900c0 0x0e407304 132*4882a593SmuzhiyunDATA 4 0x307900c0 0x0e447304 133*4882a593SmuzhiyunDATA 4 0x307900c0 0x0e447306 134*4882a593Smuzhiyun/* DDR_PHY_ZQ_CON1 */ 135*4882a593SmuzhiyunCHECK_BITS_SET 4 0x307900c4 0x1 136*4882a593Smuzhiyun/* DDR_PHY_ZQ_CON0 */ 137*4882a593SmuzhiyunDATA 4 0x307900c0 0x0e447304 138*4882a593SmuzhiyunDATA 4 0x307900c0 0x0e407304 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun/* CCM_CCGRn */ 141*4882a593SmuzhiyunDATA 4 0x30384130 0x00000000 142*4882a593Smuzhiyun/* IOMUXC_GPR_GPR8 */ 143*4882a593SmuzhiyunDATA 4 0x30340020 0x00000178 144*4882a593Smuzhiyun/* CCM_CCGRn */ 145*4882a593SmuzhiyunDATA 4 0x30384130 0x00000002 146*4882a593Smuzhiyun/* DDR_PHY_LP_CON0 */ 147*4882a593SmuzhiyunDATA 4 0x30790018 0x0000000f 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun/* DDRC_STAT */ 150*4882a593SmuzhiyunCHECK_BITS_SET 4 0x307a0004 0x1 151