1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2013 Boundary Devices 3*4882a593Smuzhiyun * Copyright (C) 2014-2016, Toradex AG 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Device Configuration Data (DCD) 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Each entry must have the format: 10*4882a593Smuzhiyun * Addr-type Address Value 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * where: 13*4882a593Smuzhiyun * Addr-type register length (1,2 or 4 bytes) 14*4882a593Smuzhiyun * Address absolute address of the register 15*4882a593Smuzhiyun * value value to be stored in the register 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun/* 19*4882a593Smuzhiyun * DDR3 settings 20*4882a593Smuzhiyun * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), 21*4882a593Smuzhiyun * memory bus width: 64 bits x16/x32/x64 22*4882a593Smuzhiyun * MX6DL ddr is limited to 800 MHz(400 MHz clock) 23*4882a593Smuzhiyun * memory bus width: 64 bits x16/x32/x64 24*4882a593Smuzhiyun * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) 25*4882a593Smuzhiyun * memory bus width: 32 bits x16/x32 26*4882a593Smuzhiyun */ 27*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 28*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 29*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 30*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 31*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 32*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 33*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 34*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B0DS, 0x00000030 37*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B1DS, 0x00000030 38*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B2DS, 0x00000030 39*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B3DS, 0x00000030 40*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B4DS, 0x00000030 41*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B5DS, 0x00000030 42*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B6DS, 0x00000030 43*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B7DS, 0x00000030 44*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 45*4882a593Smuzhiyun/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 46*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 49*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 50*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 51*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 52*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 53*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 54*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 55*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_CAS, 0x00020030 58*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_RAS, 0x00020030 59*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 60*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 61*4882a593Smuzhiyun 62*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_RESET, 0x00020030 63*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 64*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 65*4882a593Smuzhiyun 66*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 67*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun/* (differential input) */ 70*4882a593SmuzhiyunDATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 71*4882a593Smuzhiyun/* (differential input) */ 72*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 73*4882a593Smuzhiyun/* disable ddr pullups */ 74*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 75*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 76*4882a593Smuzhiyun/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 77*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun/* Read data DQ Byte0-3 delay */ 80*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 81*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 82*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 83*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 84*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 85*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 86*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 87*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun/* 90*4882a593Smuzhiyun * MDMISC mirroring interleaved (row/bank/col) 91*4882a593Smuzhiyun */ 92*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun/* 95*4882a593Smuzhiyun * MDSCR con_req 96*4882a593Smuzhiyun */ 97*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 98