1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. 3*4882a593Smuzhiyun * (c) Copyright 2016 Topic Embedded Products. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define OPCODE_EXIT 0U 9*4882a593Smuzhiyun #define OPCODE_MASKWRITE 0U 10*4882a593Smuzhiyun #define OPCODE_MASKPOLL 1U 11*4882a593Smuzhiyun #define OPCODE_MASKDELAY 2U 12*4882a593Smuzhiyun #define OPCODE_ADDRESS_MASK (~3U) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Sentinel */ 15*4882a593Smuzhiyun #define EMIT_EXIT() OPCODE_EXIT 16*4882a593Smuzhiyun /* Opcode is in lower 2 bits of address, address is always 4-byte aligned */ 17*4882a593Smuzhiyun #define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val 18*4882a593Smuzhiyun #define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask 19*4882a593Smuzhiyun #define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Returns codes of ps7_init* */ 22*4882a593Smuzhiyun #define PS7_INIT_SUCCESS (0) 23*4882a593Smuzhiyun #define PS7_INIT_CORRUPT (1) 24*4882a593Smuzhiyun #define PS7_INIT_TIMEOUT (2) 25*4882a593Smuzhiyun #define PS7_POLL_FAILED_DDR_INIT (3) 26*4882a593Smuzhiyun #define PS7_POLL_FAILED_DMA (4) 27*4882a593Smuzhiyun #define PS7_POLL_FAILED_PLL (5) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Called by spl.c */ 30*4882a593Smuzhiyun int ps7_init(void); 31*4882a593Smuzhiyun int ps7_post_config(void); 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Defined in ps7_init_common.c */ 34*4882a593Smuzhiyun int ps7_config(unsigned long *ps7_config_init); 35