1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Timll DevKit3250 board support, SPL board configuration
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
12*4882a593Smuzhiyun #include <asm/arch/cpu.h>
13*4882a593Smuzhiyun #include <asm/arch/emc.h>
14*4882a593Smuzhiyun #include <asm/arch-lpc32xx/gpio.h>
15*4882a593Smuzhiyun #include <spl.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * SDRAM K4S561632N-LC60 settings are selected in assumption that
21*4882a593Smuzhiyun * SDRAM clock may be set up to 166 MHz, however at the moment
22*4882a593Smuzhiyun * it is 104 MHz. Most delay values are converted to be a multiple of
23*4882a593Smuzhiyun * base clock, and precise pinned values are not needed here.
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun struct emc_dram_settings dram_64mb = {
26*4882a593Smuzhiyun .cmddelay = 0x0001C000,
27*4882a593Smuzhiyun .config0 = 0x00005682,
28*4882a593Smuzhiyun .rascas0 = 0x00000302,
29*4882a593Smuzhiyun .rdconfig = 0x00000011, /* undocumented but crucial value */
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun .trp = 83333333,
32*4882a593Smuzhiyun .tras = 23809524,
33*4882a593Smuzhiyun .tsrex = 12500000,
34*4882a593Smuzhiyun .twr = 83000000, /* tWR = tRDL = 2 CLK */
35*4882a593Smuzhiyun .trc = 15384616,
36*4882a593Smuzhiyun .trfc = 15384616,
37*4882a593Smuzhiyun .txsr = 12500000,
38*4882a593Smuzhiyun .trrd = 1,
39*4882a593Smuzhiyun .tmrd = 1,
40*4882a593Smuzhiyun .tcdlr = 0,
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun .refresh = 130000, /* 800 clock cycles */
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun .mode = 0x00018000,
45*4882a593Smuzhiyun .emode = 0x02000000,
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
spl_board_init(void)48*4882a593Smuzhiyun void spl_board_init(void)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun /* First of all silence buzzer controlled by GPO_20 */
51*4882a593Smuzhiyun writel((1 << 20), &gpio->p3_outp_clr);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
54*4882a593Smuzhiyun preloader_console_init();
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun ddr_init(&dram_64mb);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /*
59*4882a593Smuzhiyun * NAND initialization is done by nand_init(),
60*4882a593Smuzhiyun * here just enable NAND SLC clocks
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun lpc32xx_slc_nand_init();
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
spl_boot_device(void)65*4882a593Smuzhiyun u32 spl_boot_device(void)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun return BOOT_DEVICE_NAND;
68*4882a593Smuzhiyun }
69