1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Embest/Timll DevKit3250 board support 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun #include <asm/arch/sys_proto.h> 11*4882a593Smuzhiyun #include <asm/arch/clk.h> 12*4882a593Smuzhiyun #include <asm/arch/cpu.h> 13*4882a593Smuzhiyun #include <asm/arch/emc.h> 14*4882a593Smuzhiyun #include <asm/arch/wdt.h> 15*4882a593Smuzhiyun #include <asm/io.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; 20*4882a593Smuzhiyun static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; 21*4882a593Smuzhiyun static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE; 22*4882a593Smuzhiyun reset_periph(void)23*4882a593Smuzhiyunvoid reset_periph(void) 24*4882a593Smuzhiyun { 25*4882a593Smuzhiyun /* This function resets peripherals by triggering RESOUT_N */ 26*4882a593Smuzhiyun setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); 27*4882a593Smuzhiyun writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl); 28*4882a593Smuzhiyun udelay(300); 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun writel(0, &wdt->mctrl); 31*4882a593Smuzhiyun clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Such a long delay is needed to initialize SMSC phy */ 34*4882a593Smuzhiyun udelay(10000); 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun board_early_init_f(void)37*4882a593Smuzhiyunint board_early_init_f(void) 38*4882a593Smuzhiyun { 39*4882a593Smuzhiyun lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); 40*4882a593Smuzhiyun lpc32xx_i2c_init(1); 41*4882a593Smuzhiyun lpc32xx_i2c_init(2); 42*4882a593Smuzhiyun lpc32xx_ssp_init(); 43*4882a593Smuzhiyun lpc32xx_mac_init(); 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * nWP may be controlled by GPO19, but unpopulated by default R23 47*4882a593Smuzhiyun * makes no sense to configure this GPIO level, nWP is always high 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun lpc32xx_slc_nand_init(); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun return 0; 52*4882a593Smuzhiyun } 53*4882a593Smuzhiyun board_init(void)54*4882a593Smuzhiyunint board_init(void) 55*4882a593Smuzhiyun { 56*4882a593Smuzhiyun /* adress of boot parameters */ 57*4882a593Smuzhiyun gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #ifdef CONFIG_SYS_FLASH_CFI 60*4882a593Smuzhiyun /* Use 16-bit memory interface for NOR Flash */ 61*4882a593Smuzhiyun emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Change the NOR timings to optimum value to get maximum bandwidth */ 64*4882a593Smuzhiyun emc->stat[0].waitwen = EMC_STAT_WAITWEN(1); 65*4882a593Smuzhiyun emc->stat[0].waitoen = EMC_STAT_WAITOEN(0); 66*4882a593Smuzhiyun emc->stat[0].waitrd = EMC_STAT_WAITRD(12); 67*4882a593Smuzhiyun emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12); 68*4882a593Smuzhiyun emc->stat[0].waitwr = EMC_STAT_WAITWR(5); 69*4882a593Smuzhiyun emc->stat[0].waitturn = EMC_STAT_WAITTURN(2); 70*4882a593Smuzhiyun #endif 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun return 0; 73*4882a593Smuzhiyun } 74*4882a593Smuzhiyun dram_init(void)75*4882a593Smuzhiyunint dram_init(void) 76*4882a593Smuzhiyun { 77*4882a593Smuzhiyun gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 78*4882a593Smuzhiyun CONFIG_SYS_SDRAM_SIZE); 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun return 0; 81*4882a593Smuzhiyun } 82