1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * mux.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
7*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
8*4882a593Smuzhiyun * published by the Free Software Foundation version 2.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty
12*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13*4882a593Smuzhiyun * GNU General Public License for more details.
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <common.h>
17*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
18*4882a593Smuzhiyun #include <asm/arch/hardware.h>
19*4882a593Smuzhiyun #include <asm/arch/mux.h>
20*4882a593Smuzhiyun #include <asm/io.h>
21*4882a593Smuzhiyun #include <i2c.h>
22*4882a593Smuzhiyun #include "evm.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static struct module_pin_mux uart0_pin_mux[] = {
25*4882a593Smuzhiyun {OFFSET(pincntl70), PULLUP_EN | MODE(0x01)}, /* UART0_RXD */
26*4882a593Smuzhiyun {OFFSET(pincntl71), PULLUP_EN | MODE(0x01)}, /* UART0_TXD */
27*4882a593Smuzhiyun {-1},
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static struct module_pin_mux mmc1_pin_mux[] = {
31*4882a593Smuzhiyun {OFFSET(pincntl1), PULLUP_EN | MODE(0x01)}, /* SD1_CLK */
32*4882a593Smuzhiyun {OFFSET(pincntl2), PULLUP_EN | MODE(0x01)}, /* SD1_CMD */
33*4882a593Smuzhiyun {OFFSET(pincntl3), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[0] */
34*4882a593Smuzhiyun {OFFSET(pincntl4), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[1] */
35*4882a593Smuzhiyun {OFFSET(pincntl5), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[2] */
36*4882a593Smuzhiyun {OFFSET(pincntl6), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[3] */
37*4882a593Smuzhiyun {OFFSET(pincntl74), PULLUP_EN | MODE(0x40)}, /* SD1_POW */
38*4882a593Smuzhiyun {OFFSET(pincntl75), MODE(0x40)}, /* SD1_SDWP */
39*4882a593Smuzhiyun {OFFSET(pincntl80), PULLUP_EN | MODE(0x02)}, /* SD1_SDCD */
40*4882a593Smuzhiyun {-1},
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static struct module_pin_mux enet_pin_mux[] = {
44*4882a593Smuzhiyun {OFFSET(pincntl232), MODE(0x01)}, /* EMAC_RMREFCLK */
45*4882a593Smuzhiyun {OFFSET(pincntl233), PULLUP_EN | MODE(0x01)}, /* MDCLK */
46*4882a593Smuzhiyun {OFFSET(pincntl234), PULLUP_EN | MODE(0x01)}, /* MDIO */
47*4882a593Smuzhiyun {OFFSET(pincntl235), MODE(0x01)}, /* EMAC[0]_MTCLK */
48*4882a593Smuzhiyun {OFFSET(pincntl236), MODE(0x01)}, /* EMAC[0]_MCOL */
49*4882a593Smuzhiyun {OFFSET(pincntl237), MODE(0x01)}, /* EMAC[0]_MCRS */
50*4882a593Smuzhiyun {OFFSET(pincntl238), MODE(0x01)}, /* EMAC[0]_MRXER */
51*4882a593Smuzhiyun {OFFSET(pincntl239), MODE(0x01)}, /* EMAC[0]_MRCLK */
52*4882a593Smuzhiyun {OFFSET(pincntl240), MODE(0x01)}, /* EMAC[0]_MRXD[0] */
53*4882a593Smuzhiyun {OFFSET(pincntl241), MODE(0x01)}, /* EMAC[0]_MRXD[1] */
54*4882a593Smuzhiyun {OFFSET(pincntl242), MODE(0x01)}, /* EMAC[0]_MRXD[2] */
55*4882a593Smuzhiyun {OFFSET(pincntl243), MODE(0x01)}, /* EMAC[0]_MRXD[3] */
56*4882a593Smuzhiyun {OFFSET(pincntl244), MODE(0x01)}, /* EMAC[0]_MRXD[4] */
57*4882a593Smuzhiyun {OFFSET(pincntl245), MODE(0x01)}, /* EMAC[0]_MRXD[5] */
58*4882a593Smuzhiyun {OFFSET(pincntl246), MODE(0x01)}, /* EMAC[0]_MRXD[6] */
59*4882a593Smuzhiyun {OFFSET(pincntl247), MODE(0x01)}, /* EMAC[0]_MRXD[7] */
60*4882a593Smuzhiyun {OFFSET(pincntl248), MODE(0x01)}, /* EMAC[0]_MRXDV */
61*4882a593Smuzhiyun {OFFSET(pincntl249), MODE(0x01)}, /* EMAC[0]_GMTCLK */
62*4882a593Smuzhiyun {OFFSET(pincntl250), MODE(0x01)}, /* EMAC[0]_MTXD[0] */
63*4882a593Smuzhiyun {OFFSET(pincntl251), MODE(0x01)}, /* EMAC[0]_MTXD[1] */
64*4882a593Smuzhiyun {OFFSET(pincntl252), MODE(0x01)}, /* EMAC[0]_MTXD[2] */
65*4882a593Smuzhiyun {OFFSET(pincntl253), MODE(0x01)}, /* EMAC[0]_MTXD[3] */
66*4882a593Smuzhiyun {OFFSET(pincntl254), MODE(0x01)}, /* EMAC[0]_MTXD[4] */
67*4882a593Smuzhiyun {OFFSET(pincntl255), MODE(0x01)}, /* EMAC[0]_MTXD[5] */
68*4882a593Smuzhiyun {OFFSET(pincntl256), MODE(0x01)}, /* EMAC[0]_MTXD[6] */
69*4882a593Smuzhiyun {OFFSET(pincntl257), MODE(0x01)}, /* EMAC[0]_MTXD[7] */
70*4882a593Smuzhiyun {OFFSET(pincntl258), MODE(0x01)}, /* EMAC[0]_MTXEN */
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
enable_uart0_pin_mux(void)73*4882a593Smuzhiyun void enable_uart0_pin_mux(void)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun configure_module_pin_mux(uart0_pin_mux);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
enable_mmc1_pin_mux(void)78*4882a593Smuzhiyun void enable_mmc1_pin_mux(void)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun configure_module_pin_mux(mmc1_pin_mux);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
enable_enet_pin_mux(void)83*4882a593Smuzhiyun void enable_enet_pin_mux(void)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun configure_module_pin_mux(enet_pin_mux);
86*4882a593Smuzhiyun }
87