1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * evm.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Board functions for TI814x EVM
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <cpsw.h>
13*4882a593Smuzhiyun #include <errno.h>
14*4882a593Smuzhiyun #include <spl.h>
15*4882a593Smuzhiyun #include <asm/arch/cpu.h>
16*4882a593Smuzhiyun #include <asm/arch/hardware.h>
17*4882a593Smuzhiyun #include <asm/arch/omap.h>
18*4882a593Smuzhiyun #include <asm/arch/ddr_defs.h>
19*4882a593Smuzhiyun #include <asm/arch/clock.h>
20*4882a593Smuzhiyun #include <asm/arch/gpio.h>
21*4882a593Smuzhiyun #include <asm/arch/mmc_host_def.h>
22*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
23*4882a593Smuzhiyun #include <asm/io.h>
24*4882a593Smuzhiyun #include <asm/emif.h>
25*4882a593Smuzhiyun #include <asm/gpio.h>
26*4882a593Smuzhiyun #include "evm.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* UART Defines */
33*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD
34*4882a593Smuzhiyun static const struct cmd_control evm_ddr2_cctrl_data = {
35*4882a593Smuzhiyun .cmd0csratio = 0x80,
36*4882a593Smuzhiyun .cmd0iclkout = 0x00,
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun .cmd1csratio = 0x80,
39*4882a593Smuzhiyun .cmd1iclkout = 0x00,
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun .cmd2csratio = 0x80,
42*4882a593Smuzhiyun .cmd2iclkout = 0x00,
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static const struct emif_regs evm_ddr2_emif0_regs = {
46*4882a593Smuzhiyun .sdram_config = 0x40801ab2,
47*4882a593Smuzhiyun .ref_ctrl = 0x10000c30,
48*4882a593Smuzhiyun .sdram_tim1 = 0x0aaaf552,
49*4882a593Smuzhiyun .sdram_tim2 = 0x043631d2,
50*4882a593Smuzhiyun .sdram_tim3 = 0x00000327,
51*4882a593Smuzhiyun .emif_ddr_phy_ctlr_1 = 0x00000007
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static const struct emif_regs evm_ddr2_emif1_regs = {
55*4882a593Smuzhiyun .sdram_config = 0x40801ab2,
56*4882a593Smuzhiyun .ref_ctrl = 0x10000c30,
57*4882a593Smuzhiyun .sdram_tim1 = 0x0aaaf552,
58*4882a593Smuzhiyun .sdram_tim2 = 0x043631d2,
59*4882a593Smuzhiyun .sdram_tim3 = 0x00000327,
60*4882a593Smuzhiyun .emif_ddr_phy_ctlr_1 = 0x00000007
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun const struct dmm_lisa_map_regs evm_lisa_map_regs = {
64*4882a593Smuzhiyun .dmm_lisa_map_0 = 0x00000000,
65*4882a593Smuzhiyun .dmm_lisa_map_1 = 0x00000000,
66*4882a593Smuzhiyun .dmm_lisa_map_2 = 0x806c0300,
67*4882a593Smuzhiyun .dmm_lisa_map_3 = 0x806c0300,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun static const struct ddr_data evm_ddr2_data = {
71*4882a593Smuzhiyun .datardsratio0 = ((0x35<<10) | (0x35<<0)),
72*4882a593Smuzhiyun .datawdsratio0 = ((0x20<<10) | (0x20<<0)),
73*4882a593Smuzhiyun .datawiratio0 = ((0<<10) | (0<<0)),
74*4882a593Smuzhiyun .datagiratio0 = ((0<<10) | (0<<0)),
75*4882a593Smuzhiyun .datafwsratio0 = ((0x90<<10) | (0x90<<0)),
76*4882a593Smuzhiyun .datawrsratio0 = ((0x50<<10) | (0x50<<0)),
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
set_uart_mux_conf(void)79*4882a593Smuzhiyun void set_uart_mux_conf(void)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun /* Set UART pins */
82*4882a593Smuzhiyun enable_uart0_pin_mux();
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
set_mux_conf_regs(void)85*4882a593Smuzhiyun void set_mux_conf_regs(void)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun /* Set MMC pins */
88*4882a593Smuzhiyun enable_mmc1_pin_mux();
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* Set Ethernet pins */
91*4882a593Smuzhiyun enable_enet_pin_mux();
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
sdram_init(void)94*4882a593Smuzhiyun void sdram_init(void)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun config_dmm(&evm_lisa_map_regs);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
99*4882a593Smuzhiyun &evm_ddr2_emif0_regs, 0);
100*4882a593Smuzhiyun config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
101*4882a593Smuzhiyun &evm_ddr2_emif1_regs, 1);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun #endif
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /*
106*4882a593Smuzhiyun * Basic board specific setup. Pinmux has been handled already.
107*4882a593Smuzhiyun */
board_init(void)108*4882a593Smuzhiyun int board_init(void)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
111*4882a593Smuzhiyun return 0;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun #if defined(CONFIG_MMC)
board_mmc_init(bd_t * bis)115*4882a593Smuzhiyun int board_mmc_init(bd_t *bis)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun omap_mmc_init(1, 0, 0, -1, -1);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun return 0;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun #endif
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_CPSW
cpsw_control(int enabled)124*4882a593Smuzhiyun static void cpsw_control(int enabled)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun /* VTP can be added here */
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun return;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun static struct cpsw_slave_data cpsw_slaves[] = {
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun .slave_reg_ofs = 0x50,
134*4882a593Smuzhiyun .sliver_reg_ofs = 0x700,
135*4882a593Smuzhiyun .phy_addr = 1,
136*4882a593Smuzhiyun },
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun .slave_reg_ofs = 0x90,
139*4882a593Smuzhiyun .sliver_reg_ofs = 0x740,
140*4882a593Smuzhiyun .phy_addr = 0,
141*4882a593Smuzhiyun },
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun static struct cpsw_platform_data cpsw_data = {
145*4882a593Smuzhiyun .mdio_base = CPSW_MDIO_BASE,
146*4882a593Smuzhiyun .cpsw_base = CPSW_BASE,
147*4882a593Smuzhiyun .mdio_div = 0xff,
148*4882a593Smuzhiyun .channels = 8,
149*4882a593Smuzhiyun .cpdma_reg_ofs = 0x100,
150*4882a593Smuzhiyun .slaves = 1,
151*4882a593Smuzhiyun .slave_data = cpsw_slaves,
152*4882a593Smuzhiyun .ale_reg_ofs = 0x600,
153*4882a593Smuzhiyun .ale_entries = 1024,
154*4882a593Smuzhiyun .host_port_reg_ofs = 0x28,
155*4882a593Smuzhiyun .hw_stats_reg_ofs = 0x400,
156*4882a593Smuzhiyun .bd_ram_ofs = 0x2000,
157*4882a593Smuzhiyun .mac_control = (1 << 5),
158*4882a593Smuzhiyun .control = cpsw_control,
159*4882a593Smuzhiyun .host_port_num = 0,
160*4882a593Smuzhiyun .version = CPSW_CTRL_VERSION_1,
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun #endif
163*4882a593Smuzhiyun
board_eth_init(bd_t * bis)164*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun uint8_t mac_addr[6];
167*4882a593Smuzhiyun uint32_t mac_hi, mac_lo;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
170*4882a593Smuzhiyun printf("<ethaddr> not set. Reading from E-fuse\n");
171*4882a593Smuzhiyun /* try reading mac address from efuse */
172*4882a593Smuzhiyun mac_lo = readl(&cdev->macid0l);
173*4882a593Smuzhiyun mac_hi = readl(&cdev->macid0h);
174*4882a593Smuzhiyun mac_addr[0] = mac_hi & 0xFF;
175*4882a593Smuzhiyun mac_addr[1] = (mac_hi & 0xFF00) >> 8;
176*4882a593Smuzhiyun mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
177*4882a593Smuzhiyun mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
178*4882a593Smuzhiyun mac_addr[4] = mac_lo & 0xFF;
179*4882a593Smuzhiyun mac_addr[5] = (mac_lo & 0xFF00) >> 8;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun if (is_valid_ethaddr(mac_addr))
182*4882a593Smuzhiyun eth_env_set_enetaddr("ethaddr", mac_addr);
183*4882a593Smuzhiyun else
184*4882a593Smuzhiyun printf("Unable to read MAC address. Set <ethaddr>\n");
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun return cpsw_register(&cpsw_data);
188*4882a593Smuzhiyun }
189